KR940003411B1 - Memory core circuit of sram - Google Patents

Abstract

The memory core circuit comprises data bus lines, word lines, bit lines, and a memory cell array, a first NAND gate for receiving the output of a Y-decoder and a write enable signal, a second NAND gate for receiving the output of the Y-decoder and an inverted write enable signal, a pull-up device for receiving the output of the first NAND gate and consisting of n-channel MOSFETs, and a Y-transmission gate made up of n-channel MOSFETs and p-channel MOSFETs for receiving the inverted output of the first NAND gate and the output of the second NAND gate, thereby reducing the consumption of power.

Description

SRAM memory core circuit

1 is a circuit diagram of a conventional memory core circuit.

2 is a block diagram of a memory core circuit according to the present invention.

3a, b are circuit diagrams of a Y-decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

Q1 to Q6, Q11 to Q16: MOSFET

11: memory cell 12: pull-up unit

13: Y-transfer gate circuit 14,16: NAND gate

15,17: Inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory core circuit in which an SRAM cuts off the DC current in a write operation state, thereby reducing the total current consumption.

FIG. 1 is a circuit diagram of a conventional memory core circuit. The configuration of a memory core circuit of an SRAM includes a word line and a bit line as shown in FIG. A memory cell array 1 connected to each of the bit lines Bit line pull-up transistors Q1 and Q2 connected to the bit line, and the bit line. And data bus lines It is composed of Y-Transfer Gate (Q3 to Q6) to connect the.

Specific word line is selected by X-decoder and output of Y-decoder Once this is determined, the specific bit line This selection enables the operation of the specific cell 1, that is, write and read operations. In the read operation, the data of the selected specific cell 1 is transferred to the data bus line. To the sense amplifier, and in the write operation the output through the data input buffer Is entered into this particular cell.

However, the output data of the data input buffer during the write operation Are always opposite to each other, so the output data of the data input buffer One of them always has a value of logic "0" and the output data of the data input buffer of "0" is the data bus. The current path is formed through one of the bit line pull-up transistors Q1 and Q2 that are always on through one of the Y transfer gates and one of the Y transfer gates. there was.

The present invention devised to solve the above problems is to provide a memory core circuit for reducing the total current consumption by blocking the consumption of DC current in the write operation state by distinguishing the Y-decoder into a read and write operation state There is this.

In order to achieve the above object, the present invention provides a data bus line to which data is transferred, a word line connected to an X-decoder, a bit line selected by a Y-decoder, and a memory cell array connected to the word line and a bit line. In the memory core circuit of the configured SRAM, first negative logic means for inputting the output of the Y decoder and the write enable signal, and second negative logic for inputting the write enable signal inverted with the output of the Y decoder. A multiplying means, a pull-up means composed of an n-channel MOSFET connected to the bit line and a power source as an output of the first negative AND logic means, and an inverted output of the first negative AND logic means as a gate input and The n-channel MOSFET connected to the data bus line and the output of the second negative AND function are gate inputs, and the p-channel M connected to the bit line and the data bus line. And Y transfer gate means composed of OSFETs.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a configuration diagram of a memory core circuit according to the present invention, and 3a and b are circuit diagrams of a Y-decoder according to the present invention, 11 is a memory cell, 12 is a pull-up part, 13 is a Y-transfer gate circuit, 14, 16 is a NAND gate, 15 and 17 are inverters, and Q11 to Q16 are MOSFETs, respectively.

The memory core circuit of the SRAM according to the present invention has a word line and a bit line as shown in FIGS. 2 and 3a and b. Memory cell 11, pull-up section 12, Y-transfer gate circuit 13, and Y-decoder (Figs. 3a and b).

The Y-decoder (3a, b degrees) is a read enable signal inverted with the output (Y) of a Y-predecoder (not shown). The inverter 15 is connected to the output terminal Yr of the NAND gate 14 which is inputted as an input, and the NAND gate 15 of which the output Y of the Y-predecoder and the read enable signal WE are input. Output The inverter 17 is connected to the configuration.

The pull-up unit 12 connects a drain to a power supply Vdd and bit line The source of the NAND gate 16 And n-channel MOSFETs Q11 and Q12 connected to each other, 2 p-channel MOSFETs having a drain connected to the source, a source connected to the power supply Vdd, and an output terminal Yw of the inverter 17 connected to the gate.

The Y-transfer gate circuit 13 has a source connected to the bit line BIT, the output Yr of the NAND gate 14 as a gate input, and a drain to a data bus line DB to which data is transferred. An n-channel MOSFET having a data drain connected to the p-channel MOSFET Q15 and the bit line BIT, the output Yw of the inverter 17 serving as a gate input, and a source connected to the data bus line DB. Q13), the bit line Drain is connected to the output Yw of the inverter 17 as a gate input and the data bus line An n-channel MOSFET Q14 having a source connected to it, and the bit line It is composed of a p-channel MOSFET Q16 having a source connected to the NAND gate 14 and a output Yr of the NAND gate 14 as a gate input, and a drain connected to the data bus line DB.

The operation of the memory core circuit of the SRAM configured as described above is as follows.

The Y-decoder is an output (Y) of the Y-predecoder and a write enable signal. Is logically combined through the NAND gates 14 and 15 and the inverters 15 and 17 to operate in a write operation state. And signal operated in read operation state To adjust the Y-transmission gate by making each of them as described with reference to Table 1 below.

TABLE 1

"D" here represents a don't care state.

As shown in Table 1, the output enable signal of the Y-predecoder is Y and is inverted. Is "0", that is, the specific bit line Is selected and in the write operation state, the outputs Yw and Yr of the Y-decoder are both "1". If the outputs Yw and Yr of the Y-decoder are both "1", the p-channel MOSFETs Q15 and Q16 are turned off and the n-channel MOSFETs Q13 and Q14 are turned on to turn on the data bus line. Each bitline from Write data, and output the Y-decoder Since is "0", the n-channel MOSFETs Q11 and Q12 of the bit line pull-up section 12 are turned off to cut off the DC current source so that there is no power consumption.

Also, the output of the Y-free decoder (Y) is "1" and the inverted write enable signal is inverted. Is "1", that is, the specific bit line Is selected and in the read operation state, the Y-decoder outputs (Yw and Yr) are all "0". When the outputs Yw and Yr of the Y-decores are all "0", the n-channel MOSFETs Q13 and Q14 are turned off and the p-channel MOSFETs Q15 and Q16 are turned on to each of the bit lines. From the data bus line Reads data, and outputs the Y-decoder Since " 1 ", the n-channel MOSFETs Q11 and Q12 of the bit line pull-up section 12 are turned on to function as bit line pull-ups.

In addition, when the output Y of the Y-pre decoder is "0", the inverted write enable signal is inverted. The Y-decoder outputs (Yw, Yr) become "0" and "1" regardless of the state, and the MOSFETs (Q13, Q14, Q15, Q16) are all turned off and the bit line And data bus lines Connection with the output of the Y-decoder Is "1", the n-channel MOSFETs Q11 and Q12 are turned on so that the bit line Precharge

The present invention constructed and operated as described above uses a method of selecting the same Y-transfer gate as in the prior art, thereby reducing power consumption by cutting off current consumption during a write operation, thereby reducing power consumption. It has a very useful application effect in product design.

Claims (2)

Data bus line to which data is carried , Word line connected to X-decoder, bit line selected by Y-decoder Word line and bit line In the memory core circuit of the SRAM consisting of a memory cell array (11) connected to; A first negative logical multiplication means 16 for inputting the output Y of the Y-decoder and the write enable signal WE, and the write enable signal inverted from the output Y of the Y-decoder. Output of the second negative logical product means 14, the first negative logical product means 16 Is a gate input and the bit line A pull-up means 12 composed of n-channel MOSFETs Q11 and Q12 connected to a power supply Vdd, and an inverted output Yw of the first negative AND product 16 as a gate input. And data bus lines N-channel MOSFETs Q13 and Q14 coupled to the output Yr of the second negative AND function 14 as gate inputs and And data bus lines And a Y-transfer gate means (13) composed of p-channel MOSFETs (Q15, Q16) connected to the memory core circuit. 2. The bit line according to claim 1, wherein the pull-up means (12) uses the inverted output (Yw) of the first negative logical multiplication means (16) as a gate input. And a p-channel MOSFET connected to a power supply (Vdd).