KR940003012A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940003012A
KR940003012A KR1019920013345A KR920013345A KR940003012A KR 940003012 A KR940003012 A KR 940003012A KR 1019920013345 A KR1019920013345 A KR 1019920013345A KR 920013345 A KR920013345 A KR 920013345A KR 940003012 A KR940003012 A KR 940003012A
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KR
South Korea
Prior art keywords
conductive layer
capacitor
etching
dielectric film
forming
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Application number
KR1019920013345A
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Korean (ko)
Inventor
박흥규
허노현
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920013345A priority Critical patent/KR940003012A/en
Publication of KR940003012A publication Critical patent/KR940003012A/en

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Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 반도체기판상에 커패시터의 제1전극으로 사용되는 제1도전층을 형성하는 공정: 상기 제1도전층위에 ONO구조 유전체막을 형성하는 공정: 상기 유전체막위에 커패시터의 제2전극으로 사용되는 제2도전층을 형성하는 공정 : 및 상기 제2도전층, ONO구조 유전체막 및 제 1도전층을 식각 하여 커패시터를 형성하는 공정을 구비하는 반도체장치의 제조방법에 있어서, 상기 제2도전층, ONO구조 유전체막 및 제1도전층을 식각하여 커패시터를 헝성하는 공정은, 동일한 식각장비내에서 상기 제2도전층 부터 제1도전층 까지 차례로 식각함으로써 이루어지는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a first conductive layer to be used as a first electrode of a capacitor on a semiconductor substrate: forming an ONO structure dielectric film on the first conductive layer: the dielectric film Forming a second conductive layer to be used as a second electrode of the capacitor thereon; and forming a capacitor by etching the second conductive layer, the ONO structure dielectric film, and the first conductive layer. The method of etching the second conductive layer, the ONO structure dielectric film and the first conductive layer to form a capacitor is performed by sequentially etching the second conductive layer to the first conductive layer in the same etching equipment. It is done.

따라서 본 발명의 방법은, 종래 커패시터의 형성을 위하여 장비를 옮기면서 식각공정을 실시하던 것을 단일장비내에서 처리하기 때문에, 공기 감축효과가 있고, 장비를 옮기면서 발생할 수 있는 여러가지의 오염들을 줄일수 있으며, 공정결과(헝상의 크기 및 형태)의 변동이 줄어들게 되는 효과를 가져오게 된다.Therefore, the method of the present invention, since the processing of the etching process while moving the equipment for the formation of a conventional capacitor in a single equipment, there is an air reduction effect, and can reduce various contaminations that may occur while moving the equipment, This has the effect of reducing the fluctuation of the process result (size and shape of the hunger).

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도 내지 제7도는 본 발명에 따른 ONO구조의 유전체막을 구비한 커패시터의 제조방법을 나타낸 공정순서도.3 to 7 are process flowcharts showing a method for manufacturing a capacitor having a dielectric film of an ONO structure according to the present invention.

Claims (3)

반도체기판상에 커패시터의 제 1전극으로 사용되는 제 1도전층을 형성하는 공정 ; 상기 제 1도전층위에 ONO구조 유전체 막을 형 성하는 공정 ; 상기 유전 체 막위 에 커패시터의 제2전극으로 사용되는 제2도전층을 형성하는 공정, 및 상기 제2도전층, ONO구조 유전체막 및 제1도전층을 식각하여 커패시터를 형성하는 공정을 구비하는 반도체장치의 제조방법애 있어서, 상기 제2도전층, ONO구조 유전체막 및 제1도전층을 식각하여 커패시터를 형성하는공정은, 동일한 식각장비내에서 상기 제2도전층 부터 제1도전층까지 차례로 식각함으로써 이루어지는 것을 특징으로 하는 반도체장치의 제조방법.Forming a first conductive layer to be used as a first electrode of the capacitor on the semiconductor substrate; Forming an ONO structure dielectric film on the first conductive layer; Forming a second conductive layer to be used as a second electrode of the capacitor on the dielectric film; and forming a capacitor by etching the second conductive layer, the ONO structure dielectric film, and the first conductive layer. In the manufacturing method of the device, the step of etching the second conductive layer, the ONO structure dielectric film and the first conductive layer to form a capacitor, the etching from the second conductive layer to the first conductive layer in sequence in the same etching equipment. The semiconductor device manufacturing method characterized by the above-mentioned. 제1항에 있어서, 상기 제1도전층 및 제2도전층은 불순물이 도우핑된 다결정실리콘인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the first conductive layer and the second conductive layer are polycrystalline silicon doped with impurities. 제1항에 있어서, C2F6와 He을 사용하여 산화막, 질화막 및 다결정실리콘을 동시에 식각하는 반도체 장치의 제조방법.The method of claim 1, wherein the oxide film, the nitride film, and the polysilicon are simultaneously etched using C 2 F 6 and He. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920013345A 1992-07-25 1992-07-25 Manufacturing Method of Semiconductor Device KR940003012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920013345A KR940003012A (en) 1992-07-25 1992-07-25 Manufacturing Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920013345A KR940003012A (en) 1992-07-25 1992-07-25 Manufacturing Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR940003012A true KR940003012A (en) 1994-02-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920013345A KR940003012A (en) 1992-07-25 1992-07-25 Manufacturing Method of Semiconductor Device

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KR (1) KR940003012A (en)

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