KR940002826Y1 - Magnetic tape device for seven-head drum high density - Google Patents

Abstract

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Description

Seven-Head Drum High Density Magnetic Tape Device

1 is a conventional head structure and median position diagram.

2 is a regeneration state diagram of the apparatus according to the present invention.

3 is a cross-sectional view of the device according to the present invention.

4 is a plan view of an apparatus according to the present invention.

5 is a lead / light register control block diagram.

6 is a write shift register block diagram.

7 is a lead shift register block diagram.

8 is a data latch timing diagram.

* Explanation of symbols for main parts of the drawings

1: drum 2: laser head

3: light head 4: lead head

5: tape media 6: start sensor

7: Tape media head contact device 8-15: flip flop

16: NAND Gate 17: Toggle Flip-Flop

18-31: Shift register 32-38: Octal county

A- _O : Head G _0R1 : _Oagate

G _AND1 -G _AND7 : AND gate RST: Strobe signal

I1: Inverter IE: Input Enable Terminal

OE: Output enable terminal SO: Serial output terminal

B1-B8: BP

The present invention relates to a seven-head drum high density magnetic tape device. In particular, a seven-head drum high density magnetic tape capable of increasing file density and enabling file random access (FILE RANDOM ACCESS) by installing seven heads in a drum Relates to a device.

As shown in FIG. 1 of the prior art configuration, the drum 1 is composed of an erasure head ERASEHEAD 2, nine light heads WRITE 3, and a read head 4 READ HEAD 4. , The drum (1) is installed in parallel to the tape media (TAPE HEDIA; 5), the operation state of the configuration is as follows.

In FIG. 1, at the time of writing, data A1-A9 are loaded in the tape media 5 by one bar art through nine light heads 3 in parallel.

At the time of reading, data A1-A9 is read out from the tape media 5 through nine lead heads 4 in parallel.

In the conventional technique as described above, the drum 1 and the tape media 5 are installed in parallel to be written as a data sequence in one track, so that the magnetic distance between the beats and the beats must be maintained, thereby achieving high density. It has no distance between bits, so the number of bits per unit area is small.

Accordingly, the circuit configuration of the present invention that improves the above problems will be described with reference to the accompanying drawings.

Figure 3 shows the seven-head drum high density magnetic tape device in the present invention. Looking at the connection configuration thereof, there is a start sensor (6) for setting the head (7) and the start of the drum (1). There is a tape media head contact device (7), which is a device for bringing the head (5) into close contact with the head, and a circuit capable of controlling the data input / output of the lead / write register and a shift register and lead used for writing. It includes a shift register used when the operation state and effect of the circuit configuration is described according to the accompanying drawings as follows.

The tape media head contact device 7 is not operated at the time of the forward or rewind of FIG. At the time of writing, a command is inputted and the tape media head contact device 7 is operated. The drum 1 and the tape media 5 closely contact each other as shown in the 3b diagram. When the start sensor 6 is sensed, the write data is input to the write shift register shown in FIG. 6, but if data is input to the seven shift registers, the OA gate G of the lead / write register control circuit shown in FIG. _{When the} Ride enable signal WE (WRITE ENABLE) is input to _OR1 , the output becomes "high", and the output AH of the AND gates G _AND1 -G _AND7 is flip-flop 8-1. 5), the strobe signal P _ST is input at the same time as the write command, and the buffer B1 is enabled as a signal from the start sensor 6, and the input of the NAND gate 16 (A −). Since F) is "low", the output P1 becomes "high" and the output of the buffer B1 also becomes "high" so that the outputs A-G of the AND gates G _AND1 -G _AND7 are data of FIG. As shown in the latch timing diagram, the outputs A through G are enabled in order of one bit, and are inputted to the output enable end OE of the write shift register as shown in FIG. 6 to control the serial output of the write shift register and write. input of the enable stage (IE) of the input shift register the aND gate _(AND8 G -G _AND14), and a control input of the aND gate _(AND8 G) (B - G) coming from a host (hOST) when the "high" The first 1 byte is written to the write shift register 17 at the same time as the strobe signal RST. From the second byte, the input (B-G) of the AND gate (G _AND8 ) becomes "high" in order, and the output drops to "low" so that the write shift register 18 has the write shift register 19-24 set to 1. Only after a byte is input can a byte be input again.

When the strobe RST is input once, the output A of the AND gate G _AND1 is “high” when the output A to H state of the AND gates G _AND1 to G _AND15 (see FIG. 5) is input. The outputs B-H of the remaining AND gates G _AND2 -G _AND7 become " low ", and when the strobe PST is input once again, the outputs A & B of the AND gates G _AND1 < RTI ID = 0.0 > (G _AND2 ) < / RTI > If "high" and the output (C-H) of the remaining AND gates (G _AND3 -G _AND7 ) becomes "low" and the strobe (PST) is input seven times, the output of the AND gates (G _AND1 -G _AND7 ) (A- G) is "high" and the output H of the pullup rule 15 is "low".

At this time, the output H of the flip-flop 15 is reversed by the inverter 1 to be "high" and the output P1 of the NAND gate 16 is "low".

Of "high" and the output (H) is "low" because the AND gate (G _AND1) of the flip-flop 15 to the - conditions that may be "low" the output of NAND gate 16 is input (G A) The output P1 of the NAND gate 16 is "low" until the output A becomes "low".

The lead time is inputted from the head (i) to the lead shift register shown in FIG. 7 in the reverse order of the write time and transmitted to the host in parallel.

The input and output control of the lead shift register is controlled by a signal (A) at the input enable end (IE) when the serial data is input from the head. The signal (A) enables the strobe control buffer (B2). After the counter, the output enable data (DO) is set to "high" and the parallel outputs of the output parallel data (DO-D7) are simultaneously transferred to the host, and the read shift registers 25-31 are sequentially processed according to the signals A-G. As soon as the data is read and output to the host.

Therefore, in the seven-head drum density magnetic tape device according to the present invention, the data of the tape media 5 is written / leaded in series as described above, but after the first 1-byte lead / write, the antenna processing is performed at the same speed as the parallel. Each track has a diagonal line between the beats, which prevents the poles from moving against each other, which is a special characteristic of the magnet, increasing the density, and sharing the control part of the lead / right shift register. This method has the effect of enabling file random access by reducing the volume of the memory and counting it with a gap every 7 bytes.

Claims (2)

7 heads (ga-4) on the drum (1), the start sensor (6), the tape media head contact device (7), the circuit for controlling the data input and output of the lead / write register, the shift register used during read, write In the configuration; By means of diagonally spaced beats and beats on magnetic tape tracks to prevent densities of the same polarity, which is a characteristic of magnetization, and to increase density. A seven-head drum high density magnetic tape device, characterized in that it is configured to have one possible means. The flip-flop (8-15) in which the lead / write register control circuit operates in response to the strobe signal (PST), the write enable (WE) signal and the lead enable (RE) signal are generated by the OR gate GOR1. Is applied to the inputs of the AND gates GAND1 to GAND7 focused on each input and output of the flip-flops 8 to 15, and the output H of the final flip-flop 15 is connected to the inverter I and the NAND gate (). 16) and the flip-flop 8 is input through the start sensor buffer 1, and the output A-G of the AND gate GAND1 is input to the output enable end DE of the write shift register circuit. A seven-head drum high density magnetic tape device, characterized in that it is configured to control a serial output of a writeshift register and to be input to an input enable end (IE) of the leadshift register circuit to control the input of the leadshift register circuit.