KR940002443B1 - Semiconductor package - Google Patents

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Publication number
KR940002443B1
KR940002443B1 KR1019910004603A KR910004603A KR940002443B1 KR 940002443 B1 KR940002443 B1 KR 940002443B1 KR 1019910004603 A KR1019910004603 A KR 1019910004603A KR 910004603 A KR910004603 A KR 910004603A KR 940002443 B1 KR940002443 B1 KR 940002443B1
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KR
South Korea
Prior art keywords
semiconductor package
pad
chip
lead
thermal expansion
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KR1019910004603A
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Korean (ko)
Inventor
권영도
윤석준
Original Assignee
삼성전자 주식회사
김광호
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Priority to KR1019910004603A priority Critical patent/KR940002443B1/en
Application granted granted Critical
Publication of KR940002443B1 publication Critical patent/KR940002443B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

The semiconductor device package is disclosed wherein a buffer of low thermal expansion rate is inserted into upper and lower grooves of a pad, thereby reducing the concentration of internal pressure.

Description

반도체 패키지Semiconductor package

제1a, b, c도는 종래의 반도체 패키지를 나타낸 단면구조도.1a, b and c are cross-sectional structural views showing a conventional semiconductor package.

제2도의 (a)는 이 발명에 따른 반도체 패키지의 리이드 프레임 구조도.2A is a lead frame structure diagram of a semiconductor package according to the present invention.

(b)는 (a)의 A-A선 단면도.(b) is sectional drawing along the line A-A of (a).

제3도는 이 발명에 따른 반도체 패키지의 단면구조도이다.3 is a cross-sectional view of a semiconductor package according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

30 : 리이드 프레임 31 : 패드30: lead frame 31: pad

31a,31b : 요홈 32 : 칩31a, 31b: groove 32: chip

33 : 접착제 34 : 리이드33: adhesive 34: lead

35 : 봉지수지 36 : 반도체 패키지35: sealing resin 36: semiconductor package

37 : 기판 38a,38b : 완충제37 substrate 38a, 38b buffer

이 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 반도체 패키지의 주요 구성요소인 칩, 리이드 프레임, 봉지수지등의 열팽창계수가 서로 다름으로써 반도체 패키지의 실장시 발생되는 크랙(Crack)을 방지할 수 있는 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package. More specifically, the thermal expansion coefficients of chips, lead frames, and encapsulation resins, which are the main components of the semiconductor package, are different from each other to prevent cracks generated when the semiconductor package is mounted. Relates to a semiconductor package.

일반적으로 반도체 패키지는 제1a도에 나타낸 바와같이, 평탄한 패드(1)상에 반도체 칩(2)이 접착제(3)로 부착되어 양측에 형성된 리이드(4)와 와이어 본딩되고, 봉지수지(5)로 몰딩됨으로써 반도체 패키지(6)가 제조되며, 반도체 패키지(6)의 외부로 노출된 리이드(4)를 기판(7)에 장착하여 실장하게 된다.In general, as shown in FIG. 1A, a semiconductor package is wire bonded with a lead 4 formed on both sides by an adhesive 3 attached to a semiconductor chip 2 on a flat pad 1, and an encapsulating resin 5. The semiconductor package 6 is manufactured by molding the semiconductor package 6, and the lead 4 exposed to the outside of the semiconductor package 6 is mounted on the substrate 7 to be mounted.

이와같이 제조되어 실장되는 반도체 패키지(6)는, 봉지수지(5)로 몰딩시 고온(175℃이상)으로 몰딩된후 상온으로 온도가 낮아지게 됨으로써, 칩(2), 패드(1), 리이드(4), 봉지수지(5)의 재료 특성에 의해 열수축되면서 반도체 패키지(6) 내부에 습기 및 스트레스(Stress)가 잔존하게 된다. 그리고, 상기와 같은 반도체 패키지(6)를 기판(7)상에 실장할때, 특히 표면실장시에는 고온하에서 실장이 이루어지게 되므로 반도체 패키지(6)의 내부에 잔존해 있던 습기가 열팽창하면서 증기압으로 변하게 됨으로써 스트레스가 더욱 커지게 되어 반도체 패키지(6)내의 가장 취약한 부위를 중심으로 크랙이 발생되었고, 이는 제1a도에서와 같이 패드(1)의 저면에서 본 압력이 발생되었으며, 패드(1)의 저면에서도 중심부의 압력이 가장 큰 것으로 나타났다. 따라서, 패드(1)의 저면에서 발생하는 압력을 방지하기 위해 제1b 및 c도와 같이 패드(1) 저면에 딤플(Dimple) 및 슬로트(Slot)를 형성하여 크랙을 방지하게 되었다. 먼저, 제1b도와 같이 패드(11) 저면에 딤플(11a)를 형성한 경우는, 패드(11) 저면에 형성된 딤플(11a)에 의해 봉지수지(15)와의 접착력이 강화됨으로써, 패드(11) 저면에서 발생하는 압력이 어느정도 방지되어 제1a도와 같은 평탄한 패드(1)보다 크랙이 50% 정도 저하되었다. 그러나, 패드(11) 저면에서의 크랙발생은 어느정도 방지되었으나 패드(11) 위쪽 모서리부터 상측으로의 크랙발생율은 증가하는 문제점이 발생하였다. 또한, 제1c도와 같이 패드(21)에 관통하는 다수의 슬로트(21a)를 형성한 경우는, 패드(21)에 다수의 슬로트(21a)를 형성함으로써 패드(21) 저면에서 봉지수지(25)의 기화팽창으로 발생하는 압력을 분산시키는 효과를 가지고 있으나 리이드 프레임과의 증기화 과정에서 크랙발생 정도를 비교할때 상기 큰 효과를 얻을 수 없었고, 패드(21)상에 칩(22)을 접착제(22)로 부착할때 접착제(23)가 슬로트(21a)내로 흘러들어가 제조공정상의 신뢰도를 저하시키는 또다른 문제점이 발생하였던 것이다.The semiconductor package 6 manufactured and mounted in this way is molded at a high temperature (175 ° C. or more) during molding with the encapsulation resin 5 and then cooled to room temperature, thereby reducing the chip 2, the pad 1, and the lead ( 4), moisture and stress remain in the semiconductor package 6 as it is thermally contracted by the material properties of the encapsulation resin 5. When the semiconductor package 6 is mounted on the substrate 7 as described above, especially at the time of surface mounting, the semiconductor package 6 is mounted at a high temperature, so that the moisture remaining in the semiconductor package 6 is thermally expanded and vaporized. As the stress is increased, cracks are generated around the most vulnerable portion of the semiconductor package 6, and as shown in FIG. 1A, the pressure seen from the bottom of the pad 1 is generated. At the bottom, the central pressure was the greatest. Therefore, in order to prevent pressure generated at the bottom of the pad 1, dimples and slots are formed on the bottom of the pad 1 to prevent cracks as illustrated in FIGS. 1b and c. First, in the case where the dimples 11a are formed on the bottom surface of the pad 11 as shown in FIG. 1B, the adhesive force with the encapsulating resin 15 is strengthened by the dimples 11a formed on the bottom surface of the pad 11, thereby providing the pads 11. The pressure generated at the bottom surface was prevented to some extent, and the cracks were reduced by about 50% than the flat pad 1 as shown in FIG. However, although the occurrence of cracks at the bottom of the pad 11 was prevented to some extent, there was a problem in that the occurrence rate of cracks from the upper edge of the pad 11 to the upper side was increased. In addition, in the case where a plurality of slots 21a penetrate the pad 21 as shown in FIG. 1C, a plurality of slots 21a are formed in the pad 21 to form an encapsulating resin on the bottom surface of the pad 21. 25) has the effect of dispersing the pressure generated by the expansion of the vaporization, but the large effect was not obtained when comparing the degree of cracking in the vaporization process with the lead frame, the adhesive chip 22 on the pad 21 Another problem arises in that the adhesive 23 flows into the slot 21a when attached to (22) and degrades reliability in the manufacturing process.

이 발명은 상기와 같은 문제점을 감안하여 해결하기 위한 것으로서, 이 발명의 목적은 반도체 패키지의 제조시 잔존해있던 습기 및 스트레스에 의해 반도체 패키지의 실장시 반도체 패키지내부에서 발생하는 압력을 완화시켜 크랙을 방지함으로써 제품의 불량을 줄일 수 있는 반도체 패키지를 제공함에 있다.Disclosure of Invention The present invention has been made in view of the above problems, and an object of the present invention is to relieve the pressure generated inside the semiconductor package during mounting of the semiconductor package due to moisture and stress remaining during the manufacture of the semiconductor package. The present invention provides a semiconductor package capable of preventing product defects.

상기 목적을 달성하기 위한 이 발명의 특징은, 패드상에 반도체 칩을 부착하여 리이드와 와이어 본딩한후 봉지수지로 몰딩하여 제조되는 반도체 패키지에 있어서, 상기 패드의 상, 하면에 요홈을 형성하고 요홈에 열팽창율이 낮은 완충제를 삽입시킨 반도체 패키지인 것이다.A feature of the present invention for achieving the above object is, in a semiconductor package manufactured by attaching a semiconductor chip on a pad and wire bonding with a lead and molding with an encapsulating resin, the groove is formed on the upper and lower surfaces of the pad and the groove It is a semiconductor package in which a buffer having a low thermal expansion coefficient is inserted into the same.

이하, 이 발명에 따른 실시예를 첨부도면에 의하여 상세하게 설명한다. 제2a,b도는 이 발명에 따른 반도체 패키지의 리이드 프레임 구조를 나타낸 것으로, 리이드 프레임(30)의 중앙부에 칩(32)이 부착되는 패드(31)가 형성되고, 상기 패드(31)의 주변으로 다수의 리이드(34)가 배열형성되며, 상기 패드(31)의 상, 하면 중앙부에 소정크기, 적어도 부착되어지는 칩(32)보다 작은 크기의 요홈(31a), (31b)이 각각 형성된다. 그리고, 제3도는 이 발명에 따른 반도체 패키지(36)를 나타낸 것으로, 패드(31)의 요홈(31a), (31b)에 열팽창률이 낮은 예를들면 수지류 또는 실리콘계등의 재질로된 완충제(38a), (38b)가 삽입되고, 패드(31)의 상면에 칩(32)이 접착제(33)로 부착되며, 양측의 리이드(34)와 칩(32)이 와이어 본딩된후 봉지수지(35)로 몰딩된 것이다.Hereinafter, embodiments according to the present invention will be described in detail with the accompanying drawings. 2A and 2B show a lead frame structure of a semiconductor package according to the present invention, in which a pad 31 to which a chip 32 is attached is formed at the center of the lead frame 30, and the pad 31 is surrounded by the pad 31. A plurality of leads 34 are arranged, and recesses 31a and 31b having a predetermined size and smaller size than at least the chip 32 attached to the upper and lower surfaces of the pad 31 are formed, respectively. 3 shows a semiconductor package 36 according to the present invention, in which the recesses 31a and 31b of the pad 31 have a low thermal expansion coefficient, for example, a buffer made of a material such as resin or silicon ( 38a) and 38b are inserted, the chip 32 is attached to the top surface of the pad 31 with the adhesive 33, and the lead 34 and the chip 32 of both sides are wire-bonded, and then the encapsulating resin 35 It is molded with).

이와같은 이 발명은 제3도에서와 같이 기판(37)상에 반도체 패키지(36)을 표면실장하게 되면, 반도체 패키지의 제조시 반도체 패키지(36)내에 잔존해있던 습기가 실장시의 고온에 의해 증기압으로 변하게 되어 반도체 패키지(36)내에 압력을 발생하게 된다. 이때 이와같은 압력은 패드(31)의 하부에서 크게 발생되고, 더우기 패드(31) 하부에서도 중앙부위에 가장 큰 압력이 발생하는 것이다. 패드(31)의 상, 하측에 요홈(31a)(31b)이 형성되고, 이 요홈(31a)(31b)에 열팽창이 낮은 완충제(38a)(38b)가 삽입되어 있기 때문에 이 완충제(38a)(38b)에 의해 패드(31)의 상, 하 중심부에서 발생하는 압력이 흡수되므로 반도체 패키지(38)내의 압력집중이 감소되어 크랙 발생이 방지되는 것이다.In the present invention, when the semiconductor package 36 is surface-mounted on the substrate 37 as shown in FIG. 3, the moisture remaining in the semiconductor package 36 at the time of manufacture of the semiconductor package is caused by the high temperature at the time of mounting. The pressure is changed to generate a pressure in the semiconductor package 36. At this time, such a pressure is largely generated at the lower portion of the pad 31, and moreover, the greatest pressure is generated at the central portion even in the lower portion of the pad 31. Grooves 31a and 31b are formed above and below the pad 31, and the buffers 38a and 38b having low thermal expansion are inserted into the grooves 31a and 31b. Since the pressure generated in the upper and lower center portions of the pad 31 is absorbed by the 38b), the pressure concentration in the semiconductor package 38 is reduced to prevent the occurrence of cracks.

이상에서와 같이 이 발명에 따른 반도체 장치에 의하면, 칩이 부착되는 패드의 상, 하부에 요홈이 형성되고 이 요홈에 완충제가 삽입됨으로써 반도체 패키지의 실장시 고온에 의해 발생되는 내부압력의 집중이 감소되어 반도체 패키지내의 크랙이 방지됨에 따라 제품불량의 감소로 생산성 및 신뢰성이 향상되는 효과가 있다.As described above, according to the semiconductor device according to the present invention, grooves are formed in the upper and lower portions of the pad to which the chip is attached, and the buffer is inserted into the grooves, thereby reducing the concentration of internal pressure generated by the high temperature when the semiconductor package is mounted. As the cracks in the semiconductor package are prevented, productivity and reliability are improved by reducing product defects.

Claims (2)

패드(31)상에 반도체 칩(32)을 부착하여 리이드(34)와 와이어본딩한후 봉지수지(35)로 몰딩하여 제조되는 반도체 패키지에 있어서, 상기 패드(31) 상, 하면의 요홈(31a)(31b)에 열팽창율이 낮은 완충제(38a)(38b)를 삽입시키게 됨을 특징으로 하는 반도체 패키지.In the semiconductor package manufactured by attaching the semiconductor chip 32 on the pad 31, wire bonding with the lead 34, and molding the encapsulation resin 35, grooves 31a on the top and bottom surfaces of the pad 31 are formed. And (b) a low thermal expansion coefficient (38a) (38b). 제1항에 있어서, 상기 완충제(38a)(38b)는 열팽창률이 낮은 수지류 또는 실리콘계로 된 반도체 패키지.The semiconductor package according to claim 1, wherein the buffers (38a) (38b) are made of resins or silicon-based resins having a low coefficient of thermal expansion.
KR1019910004603A 1991-03-23 1991-03-23 Semiconductor package KR940002443B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910004603A KR940002443B1 (en) 1991-03-23 1991-03-23 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004603A KR940002443B1 (en) 1991-03-23 1991-03-23 Semiconductor package

Publications (1)

Publication Number Publication Date
KR940002443B1 true KR940002443B1 (en) 1994-03-24

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Application Number Title Priority Date Filing Date
KR1019910004603A KR940002443B1 (en) 1991-03-23 1991-03-23 Semiconductor package

Country Status (1)

Country Link
KR (1) KR940002443B1 (en)

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