KR940001624Y1 - Video signal output circuit - Google Patents
Video signal output circuit Download PDFInfo
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- KR940001624Y1 KR940001624Y1 KR2019880011761U KR880011761U KR940001624Y1 KR 940001624 Y1 KR940001624 Y1 KR 940001624Y1 KR 2019880011761 U KR2019880011761 U KR 2019880011761U KR 880011761 U KR880011761 U KR 880011761U KR 940001624 Y1 KR940001624 Y1 KR 940001624Y1
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- transistor
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- resistor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
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- Multimedia (AREA)
- Signal Processing (AREA)
- Picture Signal Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 영상 출력회로도.1 is a conventional video output circuit diagram.
제2도는 본 고안의 영상 출력회로도.2 is a video output circuit diagram of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
CRT : 브라운관 P1', P1, P2: 입력단자CRT: CRT P 1 ', P 1 , P 2 : Input terminal
R1'-R4', R1-R11: 저항 Q1', Q2', Q1-Q6: 트랜지스터R 1 '-R 4 ', R 1- R 11 : resistor Q 1 ', Q 2 ', Q 1- Q 6 : transistor
C1', C1: 콘덴서 ZD1' : 제너다이오드C 1 ', C 1 : Capacitor ZD 1 ': Zener Diode
L1', L1: 코일 D1-D3: 다이오드L 1 ′, L 1 : coil D 1 -D 3 : diode
VR1: 가변저항 +Vcc1+Vcc2: 전원VR 1 : Variable resistor + Vcc 1 + Vcc 2 : Power
본 고안은 모니터 (MONITOR)에 있어서, 영상출력회로에 관한 것으로, 특히 브라운관의 캐소우드에 입력되는 영상 신호를 증폭시켜 안정화시키도록한 브라운관 캐소우드의 입력 영상출력회로에 관한 것이다.The present invention relates to an image output circuit in a MONITOR, and more particularly to an input image output circuit of a cathode ray tube cathode which amplifies and stabilizes an image signal inputted to the cathode of a cathode ray tube.
종래에는 제1도에 도시한 바와같이 입력단자(P1')를 통과한 비데오신호가 바이어스저항(R1') (R2') 및 주파수특성 결정용 콘덴서 (C1')와 접속된 트랜지스터 (Q1')를 턴온시키고, 전원(+Vcc1)이 바이어스저항(R3')과정전압용 제너다이오드(ZD1')를 턴온시켜 트랜지스터(Q2')의 콜렉터측으로부터 증폭된 파형을 출력시킨후 편향코일(L1')에 인가됨과 아울러 전원(+Vcc2)이 저항(R4')을 통하여 편향코일(L1')에 인가됨에 따라 브라운관(CRT)의 캐소우드측(K)에 영상힌호가 출력됨으로서 화면이 재생되게 하였으나, 주파수가 높게 되면, 화면이무너지게 되는 결점이 있었다.Conventionally, as shown in FIG. 1, a video signal passing through an input terminal P 1 ′ is connected to a bias resistor R 1 ′ (R 2 ′) and a capacitor C 1 ′ for determining frequency characteristics. Turn on (Q 1 ') and the power supply (+ Vcc 1 ) turn on the zener diode (ZD 1 ') for the bias resistor (R 3 ') process voltage to obtain the amplified waveform from the collector side of transistor (Q 2 '). After the output, it is applied to the deflection coil (L 1 ') and the power supply (+ Vcc 2 ) is applied to the deflection coil (L 1 ') through the resistor (R 4 ') as the cathode side (KRT) of the cathode tube (CRT) ), But the screen was played by outputting the video hint, but when the frequency was high, the screen was collapsed.
본 고안은 이와같은 종래의 결함을 감안하여 브라운관의 캐소우드측에 입력되는 영상신호를 안정되게 증폭시켜, 높은 주파수에도 화면의 찌그러짐이 방지되게 한 브라운관 캐소우드의 입력 영상출력회로를 안출한 것으로, 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.The present invention devised an input video output circuit of the cathode ray tube cathode which stably amplifies the image signal inputted to the cathode side of the cathode ray tube in order to prevent distortion of the screen even at a high frequency. When described in detail by the accompanying drawings as follows.
제2도는 본 고안의 영상출력 회로도로서 이에 도시한 바와같이, 입력단자를 통과한 비데오신호가 바이어스저항 (R1-R3)과 접속된 트랜지스터 (Q1)를 통하여 버퍼되게하고, 바이어스 저항 (R4) (R5), 가변저항 (VR1)의 조정을 통하여 트랜지스터(Q3)를 구동하게 한후 트랜지스터 (Q2)의 에미터측 저항(R3), 저항(R10) (R11), 주파수특성결정용 콘덴서(C1), 방향제어용 다이오드(D1)와 접속된 트랜지스터 (Q3)를 통하여 입력단자(P2)를 통과한 수직 및 수평 플라이백 펄스의 합성파형과 합성되게하며, 상기 트랜지스터(Q2)의 콜렉터측 증폭파형이 전원(+Vcc1)인가용 바이어스저항(R6) (R7)을 통하여 트랜지스터(Q4)를 통하여 증폭되게 하고, 전원(+Vcc2) 분배용 편향코일(L1), 바이어스저항(R9), 전압분배용 다이오드(D2) (D3)와 접속된 증폭용 트랜지스터(Q5) (Q6)를통하여 브라운관(CRT)의 캐소우드(K)에 인가되게 구성한 것이다.2 is an image output circuit diagram of the present invention, and as shown therein, the video signal passing through the input terminal is buffered through the transistor Q 1 connected to the bias resistors R 1 -R 3 , and the bias resistor ( R 4 ) (R 5 ), the transistor Q 3 is driven by adjusting the variable resistor VR 1 , and then the emitter side resistor R 3 and resistor R 10 (R 11 ) of the transistor Q 2 . By combining the frequency characteristic capacitor (C 1 ) and the direction control diode (D 1 ) and the transistor (Q 3 ) connected to the synthesized waveform of the vertical and horizontal flyback pulses passing through the input terminal (P 2 ) The amplifying waveform of the collector side of the transistor Q 2 is amplified through the transistor Q 4 through the bias resistor R 6 (R 7 ) for applying the power supply (+ Vcc 1 ), and the power supply (+ Vcc 2 ) deflection coil for distribution (L 1), a bias resistor (R 9), diodes for voltage division (D 2) (D 3) if the amplified transfected and connecting Emitter is configured to be applied to the (Q 5) cathode (K) of cathode-ray tube (CRT) via a (Q 6).
이와같이 구성된 본 고안의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured in this way in detail as follows.
제2도에 도시한 바와같이 전압레벨(V1)을 갖는 비데오신호가 입력단자(P1)에 입력되면, 바이어스 저항(R1)을 통하여 트랜지스터 (Q2)를 턴온시킴에 따라 트랜지스터(Q1)의 에미터측 저항(R3)에서 A급 증폭되고, 바이어스 저항(R4) (R5), 가변저항 (VR1)의 조정을 통하여 입력 비데오신호의 게인전압틀 조정한후 트랜지스터(Q2)를 턴온시키며, 이때 트랜지스터 (Q2)의 바이어스전원레벨(V2)이 가변저항(VR1)을 통하여 조정된다.As shown in FIG. 2, when the video signal having the voltage level V 1 is input to the input terminal P 1 , the transistor Q 2 is turned on by turning on the transistor Q 2 through the bias resistor R 1 . 1 ) Class A amplification at the emitter side resistor (R 3 ) of 1 ), and adjust the gain voltage frame of the input video signal by adjusting the bias resistor (R 4 ) (R 5 ) and the variable resistor (VR 1 ) and then the transistor (Q 2). ) Is turned on, and the bias power level V 2 of the transistor Q 2 is adjusted through the variable resistor VR 1 .
여기서 트랜지스터(Q2)의 에미터측에 인가된 비데오신호가 바이어스저항(R8)을 통하여 트랜지스터(Q3)를 턴온시킴에 따라 트랜지스터(Q3)의 에미터 저항(R10)에 인가된 후 콘덴서(C1)를 통하여 주파수특성을 결정함과 아울러 방향제어용 다이오드 (D1)를 통하여 입력단자(P2)를 통과한 수직 및 수평 플라이백펄스의 합성파형과합성되고 트랜지스터(Q2)의 콜렉터측에서 증폭된 파형의 전원(+Vcc1)과 함께 바이어스저항 (R6) (R7)을 통하여 트랜지스터(Q4)를 턴온시킴에 따라 트랜지스터(Q4)의 콜렉터측에는 반전증폭된 전압레벨(V2)을 갖는 파형이 발생되며, 이때 트랜지스터 (Q2)의 에미터 저항(R8)은 증폭 개인을, 트랜지스터 (Q3)의 에미 저항(R10)은 비데오게인을 결정한다.Here, the video signal applied to the emitter teocheuk of the transistor (Q 2) in accordance with Sikkim turning on the transistor (Q 3) via a bias resistor (R 8) after being applied to the emitter resistor (R 10) of the transistor (Q 3) a capacitor (C 1) and determines the frequency characteristics through the addition direction control diode (D 1) a via an input terminal (P 2) to pass through the vertical and horizontal flyback synthetic and composite waveform of the pulse and of the transistor (Q 2) the power of the amplified waveform in the collector side (+ Vcc 1) and with a bias resistor (R 6) (R 7) a through the transistor (Q 4) the turn-on Sikkim transistor (Q 4) the voltage level reverse side collector amplifier according to A waveform with (V 2 ) is generated, wherein the emitter resistor (R 8 ) of transistor (Q 2 ) determines the amplification individual and the emi resistor (R 10 ) of transistor (Q 3 ) determines the video gain.
이와동시에 전원(+Vcc2)이 편향코일(L1), 바이어스저항(R9), 전압분배용 다이오드(D2) (D3)를 통하여 트랜지스터 (Q5) (Q6)의 베이스측에 바이어스전원을 인가시켜 트랜지스터 (Q5) (Q6)를 턴온 시킴에 따라 트랜지스터(Q5) (Q6) 에미터측에서 전압레벨(V3)을 갖는 파형으로 변화된후 브라운관(CRT)의 캐소우드측(K)에 인가됨으로서 브라운관(CRT)의 화면이 안정되게 재생될수 있는 것이다.At the same time, the power supply (+ Vcc 2 ) is supplied to the base side of the transistors (Q 5 ) (Q 6 ) through the deflection coil (L 1 ), the bias resistor (R 9 ), and the voltage distribution diode (D 2 ) (D 3 ). As the transistor Q 5 (Q 6 ) is turned on by applying a bias power source, the cathode of the cathode ray tube (CRT) is changed into a waveform having a voltage level (V 3 ) at the emitter side of the transistor (Q 5 ) (Q 6 ). By being applied to the side K, the picture of the CRT can be stably reproduced.
즉 트랜지스터 (Q1)를 통하여 버퍼된 비데오신호가 가변저항(VR1)의 조정을 통하여 트랜지스터 (Q2)를 턴온시킨후 트랜지스터(Q)를 통하여 수직 및 수평 플라이백펄수의 합성신호와 합성됨과 아울러 트랜지스터 (Q4)를통하여 반전증폭되고, 트랜지스터 (Q5) (Q6)를 통하여 다시 증폭되어 브라운관(CRT)의 캐소우드(K)에 인가됨으로서 브라운관(CRT)의 화면이 고주파에도 화면이 인정되게 재생될수 있는 것이다.I.e., the transistor (Q 1) as soon the video signal buffers through a variable resistor (VR 1) to adjust the by then turning on the transistor (Q 2) through the transistor (Q) the vertical and horizontal flyback peolsu synthesized and the synthesized signal of the in addition, and the inverting amplifier via a transistor (Q 4), a transistor (Q 5) (Q 6) is again amplified through the screen of the cathode-ray tube by being applied to the cathode (K) of the (CRT) cathode ray tube (CRT) to high-frequency screen It can be recognized and reproduced.
이상에서 설명한 바와같이 본 고안은 주파수가 높은 주파수에도 화면의 찌그러짐이 방지될수 있는 효과가있는 것이다.As described above, the present invention has an effect of preventing distortion of the screen even at high frequencies.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR2019880011761U KR940001624Y1 (en) | 1988-07-20 | 1988-07-20 | Video signal output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR2019880011761U KR940001624Y1 (en) | 1988-07-20 | 1988-07-20 | Video signal output circuit |
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Publication Number | Publication Date |
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KR900004008U KR900004008U (en) | 1990-02-08 |
KR940001624Y1 true KR940001624Y1 (en) | 1994-03-21 |
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KR2019880011761U KR940001624Y1 (en) | 1988-07-20 | 1988-07-20 | Video signal output circuit |
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KR (1) | KR940001624Y1 (en) |
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1988
- 1988-07-20 KR KR2019880011761U patent/KR940001624Y1/en not_active IP Right Cessation
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KR900004008U (en) | 1990-02-08 |
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