KR940000206Y1 - Processor of timer command - Google Patents

Abstract

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Description

Timer command handler

1 is a circuit diagram of a PLC using a timer command processor according to an embodiment of the present invention.

2 is a detailed circuit diagram of a timing command control device according to an embodiment of the present invention.

3 is a memory map of RAM.

This invention relates to a timer instruction processor, and in particular, a timer instruction processor for processing a timer instruction among instructions of a programmable logic controller (hereinafter referred to as "PLC") represented by a ladder diagram. It is about.

In general, PLC is a device that is widely applied in the field of factory automation (FA), and it is possible to compact the functions of individual components such as relay, timer, counter, and solid-state relay in logic. It is an integrated device.

The number of timers that can be arbitrarily used by a user in the PLC is usually more than 256 (assuming 256 in the following). These 256 timers require a certain period of interruption to the microprocessor, a central processing unit ("CPU") module, which causes the microprocessor to Do the proper processing. That is, the CPU module performs a function of determining and counting software counts for each channel of 256 timers in an interrupt service routine that is performed at regular intervals. Timer count for each channel is arbitrarily controlled by the user's program.

The following is an example of a user program. The number in parentheses on the right is the clock it takes to execute the instruction. The unit is a cycle.

Execution clock = [(2 + 4 + 14 + 4 + 20 + 4 + 17) × 16 + 10 + 4 + 13 + 8 + 4 + 17] × 16 + 10 × 5 + 4 × 5 + 8 × 5 = 17646 cycles

Killing time = 17646 T cycles × 1 / 8M = 2.2msec

In the above program, TimerEnableBit is included whether or not to count timer value of each channel. That is, the content of the corresponding bit should be counted by 1. TimerPV is the area that stores the count value for each channel. Also, TimerPV contains the contents to stop counting when the count value of each channel is OFFFH.

However, the conventional method as described above has a disadvantage in that it takes about 2.2 msec of CPU time to process 256 timer channels. That is, in the case of timer processing with a 10 msec time period, 22% of CPU processing capacity is spent for the timer.

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and to provide a timer command processor which improves the processing speed of the system by reducing the time required to process the timer command to 1/2 compared to the conventional method. .

The configuration of the present invention for achieving the above object is a selection signal CS2 connected to the M / IO signal line of the CPU and the output signal line of the address latch, which becomes low when the CPU calls the timer elapsed address area. And a decoder for outputting a selection signal CS3 and a selection signal CS4 that are in a low state when the CPU calls its address area, and the selection signal lines CS2, CS3, and CS4 of the decoder and the CPU. And a timer control device connected to the read signal line and the write signal line to determine whether the count is allowed and whether the count is countable.

Preferred embodiments of this invention by the above-described configuration will be described in detail with reference to the drawings.

1 is a circuit diagram of a PLC using a timer command processor according to an embodiment of the present invention. As shown in FIG. 1, the timer command processor is connected to the M / IO signal line of the CPU 1 and the output signal line of the latch 2, so that the selection is made low when the CPU 1 calls the timer elapsed address area. A decoder 3 for outputting a selection signal CS3 and a selection signal CS4 that are in a low state when the signal CS2 and the CPU 1 call their address areas, respectively, and the selection signal line of the decoder 3; The timer control device 4 is connected to the CS2, CS3, CS4, the read signal line RD of the CPU 1, and the write signal line WR.

2 is a detailed circuit diagram of a timer control device according to an embodiment of the present invention. As shown in FIG. 2, the configuration of the timer control device 4 includes a first OR gate 41 connected to respective input terminals of the CS2 signal line and the write signal line WR of the decoder 3, and a selection signal line. A second or gate 42 having respective input terminals connected to the CS3 and the write signal line WR, and a third or gate 43 having respective input terminals connected to the selection signal line CS2 and the read signal line RD. And a first type flip-flop 44 connected with a clock terminal CK connected to the selection signal line CS4 and an input terminal D connected to the least significant bit data line DO, and data lines D0 to D7. A first shift register in which a terminal is connected, a clock terminal CLK is connected to an output terminal of the first ora gate 41, and an enable terminal LD is connected to an output terminal of the second ora gate 42. An input terminal is connected to the data line D7 to D15 and a clock terminal CLK is connected to an output terminal of the first OR gate 41. The second shift register 46 having the enable terminal LD connected to the output terminal of the second OR gate 42 and the first NAND connected to each input terminal of the data lines D0 to D7. Inputs to the second NAND gate 48 having respective input terminals connected to the gate 47 and the data lines D8 to D15, and to output terminals of the first NAND gate 47 and the second NAND gate 48. 2D connected to a NOR gate 49 having a terminal connected thereto, an input terminal D connected to an output terminal of the NOR gate 49, and a clock terminal CK connected to an output terminal of the third OR gate 43. A fourth OR gate 51 in which respective input terminals are connected to the type flip-flop 50, the output terminal Q of the 2D type flip-flop 50, and the output terminal Q of the second shift register 46. An AND gate 52 connected to an output terminal of the fourth OR gate 51 and an output terminal Q of the 1D flip-flop 44, and an AND gate 52 of the AND gate 52. Print It consists of a chair and the CPU (1) light signal (WR) a fifth Iowa gate 53 is connected to respective input terminals of a.

The operation of the timer control device 4 according to the embodiment of this invention by the above configuration is as follows. The select signal CS2 of the decoder 3 goes low when the CPU 1 calls the timer elapsed address areas 1000H to 11FFH, and the select signal CS3 and the select signal CS4 are shown in FIG. It is input from the decoder 3 so as to be in a low state, respectively, when calling the address area specified in the memory map. To help explain the operation, a user program will be described as an example. The memory map when the following user program is stored in the lab 5 is shown in FIG. Also, the number in parentheses on the right side of the user program is the clock that the instruction takes to execute. The unit is a cycle.

Execution Clock = (10 + 14 + 24 × 16) × 16 + 4 + 10 + 8 + 8 = 6596 cycles

Execution time = 6596 cycles × 1 / 8M = 830μsec

When the above step [1] of the user program is executed, 1 is latched in the 1D flip-flop 44 to enable the AND gate 52. When step [2] of the user program is executed, the contents of the 800H address in FIG. 3 are stored in the first shift register and the second shift registers 45 and 46 by the second OR gate 42. In order to execute step [3] of the user program, the CPU 1 executes a read-modify-write cycle for 1000H of FIG. 3, and executes a read-modify-write cycle. Is stored in the 2D type flip-flop 50. When the CPU 1 wants to record the increased value in successive write cycles, it is determined whether the channel 0 is allowed by the output of the second shift register 46, so that the output of the fourth OR gate 51 is high. ), The output of the timer control device 4 is fixed to the ground state by the fifth orifice gate 53 to prevent the CPU 1 from writing the increased result, and as a result, the step [3] After completion, the 1000H address of FIG. 3 is incremented by 1 only if the 800H address 0 is not 0 and the 1000H is not OFFFFH. When the above step is completed, the first or the gate 41 determines whether the count is allowed or not by one bit from the upper bit position to the lower bit position, allowing the count of the channel following the channel 1 to the output of the second shift register 46. Whether the bit is output. The above operation is repeated as in step [3] until the coefficient permitting condition stored in the first shift register and the second shift register 45 and 46 is exhausted, and the same operation as the [2] step every 16 count determinations. Repeat 16 times to count all channels. Therefore, by counting the counting program in comparison with the conventional counting method, the counting speed can be obtained more than twice at the same CPU speed as the conventional counting method.

As described above, in the embodiment of the present invention, the time required for processing the timer command through hardware processing may be reduced to 1/2 compared to the conventional method, thereby providing a timer command processor having improved processing speed of the system. This effect of this design can be used in the PLC field where a timer command processor is used.

Claims (2)

In the PLC, the selection (CS2) and the CPU (1) connected to the M / IO signal line of the CPU 1 and the output signal line of the latch 2, and brought into a low state when the CPU 1 calls the timer elapsed address area. A decoder 3 for outputting a selection signal CS3 and a selection signal CS4, each of which is in a low state when the caller calls his address area; A timer control device connected to the selection signal lines CS2, CS3, CS4 of the decoder 3 and the read signal line RD and the write signal line WR of the CPU 1 to determine whether to allow counting and to determine whether the count is countable. (4) a timer command processor characterized by the above-mentioned. 2. The timer control device (4) according to claim 1, wherein the timer control device (4) comprises a first ora gate (41) having respective input terminals connected to the selection signal line (CS2) of the decoder (3) and the write signal line (WR) of the CPU (1). Wow; A second oar gate 42 having respective input terminals connected to the selection signal line CS3 of the decoder 3 and the write signal line WR of the CPU 1; A third OR gate 43 whose input terminals are respectively connected to the selection signal line CS2 of the decoder 3 and the read signal line RD of the CPU 1; A first type flip-flop 44 connected to the signal line CS4 of the decoder 3 and having a clock terminal CK connected to the least significant bit data line D0 of the data bus; An input terminal is connected to the data lines D0 to D7, a clock terminal CLK is connected to an output terminal of the first or gate 41, and an enable terminal LD is connected to an output terminal of the second ora gate 42. A connected first shift register 45; An input terminal is connected to the data lines D8 to D15, a clock terminal CLK is connected to an output terminal of the first OR gate 41, and an enable terminal LD is connected to an output terminal of the second OR gate 42. A second shift register 46 coupled; A first NAND gate 47 having respective input terminals connected to the data lines D0 to D7; A second NAND gate 48 having respective input terminals connected to the data lines D8 to D15; A noah gate 49 having respective input terminals connected to output terminals of the first NAND gate 47 and the second NAND gate 48; A second 2D flip-flop 50 having an input terminal D connected to an output terminal of the NOR gate 49 and a clock terminal CK connected to an output terminal of the third OR gate 43; A fourth OR gate 51 connected to an output terminal Q of the 2D flip-flop 50 and an output terminal Q of the second shift register 46; An AND gate 52 having respective input terminals connected to an output terminal of the fourth OR gate 51 and an output terminal Q of the 1D flip-flop 44; A timer comprising: a fifth ORA gate 53 connected to the output terminal of the AND gate 52 and the write signal line WR of the CPU 1 to output the coefficient permission signal CA. Command handler.