KR930024322U - 디램의 비트라인 분리회로 - Google Patents

디램의 비트라인 분리회로

Info

Publication number
KR930024322U
KR930024322U KR2019920006200U KR920006200U KR930024322U KR 930024322 U KR930024322 U KR 930024322U KR 2019920006200 U KR2019920006200 U KR 2019920006200U KR 920006200 U KR920006200 U KR 920006200U KR 930024322 U KR930024322 U KR 930024322U
Authority
KR
South Korea
Prior art keywords
bit line
separation circuit
line separation
dram bit
dram
Prior art date
Application number
KR2019920006200U
Other languages
English (en)
Other versions
KR0121149Y1 (ko
Inventor
김태형
Original Assignee
엘지반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지반도체주식회사 filed Critical 엘지반도체주식회사
Priority to KR92006200U priority Critical patent/KR0121149Y1/ko
Publication of KR930024322U publication Critical patent/KR930024322U/ko
Application granted granted Critical
Publication of KR0121149Y1 publication Critical patent/KR0121149Y1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR92006200U 1992-04-15 1992-04-15 디램의 비트라인 분리회로 KR0121149Y1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92006200U KR0121149Y1 (ko) 1992-04-15 1992-04-15 디램의 비트라인 분리회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92006200U KR0121149Y1 (ko) 1992-04-15 1992-04-15 디램의 비트라인 분리회로

Publications (2)

Publication Number Publication Date
KR930024322U true KR930024322U (ko) 1993-11-27
KR0121149Y1 KR0121149Y1 (ko) 1998-08-01

Family

ID=19331754

Family Applications (1)

Application Number Title Priority Date Filing Date
KR92006200U KR0121149Y1 (ko) 1992-04-15 1992-04-15 디램의 비트라인 분리회로

Country Status (1)

Country Link
KR (1) KR0121149Y1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100642629B1 (ko) * 2000-07-15 2006-11-10 삼성전자주식회사 반도체 메모리 장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100642629B1 (ko) * 2000-07-15 2006-11-10 삼성전자주식회사 반도체 메모리 장치

Also Published As

Publication number Publication date
KR0121149Y1 (ko) 1998-08-01

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Legal Events

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A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
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Payment date: 20060320

Year of fee payment: 9

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