KR930022220A - Data transfer device from host computer to MIMD processor - Google Patents
Data transfer device from host computer to MIMD processor Download PDFInfo
- Publication number
- KR930022220A KR930022220A KR1019920006118A KR920006118A KR930022220A KR 930022220 A KR930022220 A KR 930022220A KR 1019920006118 A KR1019920006118 A KR 1019920006118A KR 920006118 A KR920006118 A KR 920006118A KR 930022220 A KR930022220 A KR 930022220A
- Authority
- KR
- South Korea
- Prior art keywords
- address
- data
- signal
- parallel processor
- host computer
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
Abstract
본 발명은 병렬 프로세서를 사용한 컴퓨터 시스템의 인터페이스 장치에 관한 것으로서, 구체적으로는 망사구조의 MIMD(multiple instruction multiple data)형 병렬 프로세서와 이를 사용하는 호스트 컴퓨터(host computer)사이의 데이타 전송을 실시간으로 제어하기 위한 인터페이스 장치에 관한 것으로 호스트 컴퓨터(1)와, 망사구조를 갖는 MIMD형 병렬 프로세서(2)와, 이 병렬 프로세서의 각 프로세싱 엘리먼트에서 처리하기 위한 데이타를 격납하는 듀얼포트 메모리(37)를 구비하여 상기 호스트 컴퓨터(1)와 병렬 프로세서(2) 사이의 데이타 전송을 관리하는 컴퓨터 인터페이스 장치에 있어서, 상기 프로세싱 엘리먼트에서 제공되는 데이타 입력준비 신호(IR-RD)를 입력하여 순차적 카운트업 신호와 어드레스 발생용 신호를 출력하는 카운터(31)와, 상기 어드레스 발생용 신호를 받아 각 프로세싱 엘리먼트에 상응하는 데이타를 지정하는 어드레스를 순차적으로 출력하는 어드레스 발생 수단과, 상기 호스트 컴퓨터(1)에서 제공되는 최근 전송 데이타의 어드레스와 상기 어드레스 발생수단에서 제공되는 어드레스 중 현대 데이타 인출용 어드레스를 비교하여 상기 메모리(37)에 데이타 저장되었는가를 판단하는 신호를 출력하는 비교수단(36)과, 상기 비교수단(36)의 출력신호에 의해 각 프로세싱 엘리먼트에 데이타 준비신호(IRS)를 차례로 제공하는 플래그 발생수단(32)을 포함하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device of a computer system using a parallel processor, and more particularly, to real-time data transmission between a multiple instruction multiple data (MIMD) parallel processor having a network structure and a host computer using the same. A host device (1), a MIMD type parallel processor (2) having a network structure, and a dual port memory (37) for storing data for processing in each processing element of the parallel processor. In the computer interface device for managing the data transfer between the host computer 1 and the parallel processor 2, the data input ready signal (IR-RD) provided from the processing element is input to the sequential count-up signal and address A counter 31 for outputting a generation signal, and the address generation scene Address generation means for successively outputting an address specifying data corresponding to each processing element by receiving a call; modern data of an address of recent transmission data provided from the host computer 1 and an address provided from the address generation means; A comparison means 36 for comparing a drawing address and outputting a signal for determining whether data has been stored in the memory 37, and a data preparation signal IRS for each processing element by an output signal of the comparison means 36; It includes a flag generating means 32 which provides in turn.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도는 본 발명의 인터페이스 장치의 회로도.3 is a circuit diagram of an interface device of the present invention.
제4도는 본 발명의 인터페이스 장치가 실시간으로 데이타 전송되는 것을 보인 도면.4 is a diagram showing that the interface device of the present invention transmits data in real time.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920006118A KR950008395B1 (en) | 1992-04-13 | 1992-04-13 | Data transferring apparatus between mimd processor and host computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920006118A KR950008395B1 (en) | 1992-04-13 | 1992-04-13 | Data transferring apparatus between mimd processor and host computer |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930022220A true KR930022220A (en) | 1993-11-23 |
KR950008395B1 KR950008395B1 (en) | 1995-07-28 |
Family
ID=19331694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920006118A KR950008395B1 (en) | 1992-04-13 | 1992-04-13 | Data transferring apparatus between mimd processor and host computer |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950008395B1 (en) |
-
1992
- 1992-04-13 KR KR1019920006118A patent/KR950008395B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950008395B1 (en) | 1995-07-28 |
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