KR930022215A - Broadcast demap to deallocate memory pages of multiprocessor computer systems - Google Patents

Abstract

A method and apparatus are disclosed for removing page table entries from multiple translation lookaside buffers (TLBs) coupled to multiple processors in a multiprocessor system. The method has a request packet for issuing a request packet by a first controller of the first TLB to remove the page table entry from the first TLB, specifying a predetermined source, a first address mode and a process identification, and a second packet. Sends a request packet to a packet-switched bus to be broadcast for a second controller coupled to the TLB, receives a request packet by the second controller on that packet-switched bus, and compares the first mode address with a process identification. Check by the second controller to determine if the second TLB includes a page table entry, complete a predetermined hold operation for the second controller, and if the page table entry is included in the second TLB, Remove the page table entry from the second TLB, issue a reply packet by the second controller to indicate completion for the first controller, and identify the source. And a step of transmitting the reply packet to exchange bus-packet has a reply packet conducted by the first controller.

Description

Broadcast demap to deallocate memory pages of multiprocessor computer systems

Since this is an open matter, no full text was included.

1 is a simplified block diagram of a multiprocessor computer system.

2 is a symbolic representation of the datacycle in a broadcast demap request.

Figure 3 also shows the time for handler initialization demap transactions.

Claims (15)

A method of removing page table entries from multiple translation look-aside buffers ("TLBs") coupled to multiple processors in a multiprocessor system having data and command packets transmitted on a packet switched bus, each processor having a respective TLB. For controlling reads and writes, wherein the page table entry indicates an address mapping between a first address mode and a second address mode, wherein the page table entry is identified by its first mode address and process identification. A method of removing page table entries, comprising: providing a page table entry for an invalid address mapping between the first address mode and the second address mode in a first TLB coupled to a first processor; Request packets by the first controller of the first TLB to be removed from the first TLB. Issuing, sending the request packet to the packet-switched bus to be forwarded to a second controller coupled to a second TLB, having the request packet specifying a predetermined source, the first address mode and processing identification; Receiving the request packet by the second controller on the packet-switched bus, comparing the first mode address with the process identification to determine whether the second TLB includes the page table entry Checking by the controller, completing a predetermined hold operation for the second controller, and if the page table entry is included in the second TLB, the page table entry from the second TLB by the second controller. Removing a message, issuing a reply packet by the second controller to indicate completion of the first controller, And sending a reply packet to the packet-switched bus to be forwarded to the first controller with a reply packet identifying the source. 2. The method of claim 1, wherein the request packet receiving step has a reply packet specifying the source, and sending a reply packet by the second controller to the first controller when receiving the request packet via the packet switched bus. And removing the page table entry. 3. The method of claim 2, wherein issuing the request packet further includes transmitting a header and a data cycle, wherein the header cycle specifies the predetermined destination and source, and the data cycle is the page table entry. And removing the first mode address and process identification of the apparatus. 4. The method of claim 3, further comprising seating on the packet-switched bus by the first controller for a reply packet with the source. 5. The method of claim 4, wherein the first mode address and the second mode address are virtual addresses and physical addresses, respectively. 2. The system of claim 1, wherein the request packet is transmitted via the packet switched bus to all other controllers coupled to the packet switched bus, wherein all other controllers are seated on the packet-switched bus for the predetermined destination. Removing a page entry. 7. The method of claim 6 wherein the predetermined destination is indicated by all zeros in the request packet. A circuit for removing one of a plurality of page table entries from a plurality of translation lookaside buffers coupled to a plurality of processors in a multiprocessor system with distributed memory, each translation lookaside buffer storing multiple page table entries and Wherein, each of the plurality of page table entries indicates a virtual-physical address mapping, and wherein each page table entry removes one of the table entries identified by its processing identifier and virtual address, the data and command packets A packet switched bus for coupling the plurality of processors in the multiprocessor system, and a packet-switched bus for transmitting data and command packets, and transmission and reception means coupled to each processor. The receiving means is said packet for data and command packets. Having its corresponding processor on the switched bus and having a destination address, said sending and receiving means for receiving data and command packets having a predetermined destination address, said sending and receiving means switching said packet upon receipt of said request A controller means for issuing a first reply packet to the bus and coupled to a translation lookaside buffer corresponding to the transmitting and receiving means of each processor, the controller means for reading and writing its translation lookaside buffer, the controller means Issue a request packet to remove the page table when the corresponding virtual-physical address mapping is invalidated from the plurality of translation lookaside buffers having the page table entry, and indicate that the page table entry has been removed. We issue answer packet to Circuit for removing one of a number of table entries. A device for removing page table entries from multiple translation look-aside buffers (TLBs) coupled to multiple processors in a multiprocessor system having data and instruction packets transmitted on a packet switched bus, each processor for each TLB. And a controller controlling reads and writes, the page table entry indicating addresser mapping between a first address mode and a second address mode, the page table entry identified by its first mode address and process identification And a page table entry removing device having an invalid address mapping between the first address mode and the second address mode in a first TLB coupled to the first processor. 1 request by the first controller of the first TLB to remove from the TLB Means for issuing a kit, means for transmitting the request packet to the packet-switched bus to be directed to a second controller coupled to a second TLB having a predetermined source, the first address mode and the request packet specifying the process identification. Means for receiving the request packet by the second controller for the packet-switched bus, and comparing the first mode address with the process identification to determine whether the second TLB includes the page table entry Comparison means coupled to two controllers, means for completing a predetermined hold operation for the second controller, and if the page table entry is included in the second TLB, the page table entry from the second TLB by the second controller Means for issuing a reply packet by the second controller to indicate completion of the first controller; And means for transmitting a reply packet to the packet-switched bus to be forwarded to the first controller, the reply packet identifying the source. 10. The apparatus of claim 9, wherein the receiving means has the reply packet specifying the source and sends a reply packet by the second controller to the first controller when receiving the request packet via the packet switched bus. And page means for removing a page table entry. 11. The method of claim 10, wherein the means for delivering further comprises means for transmitting a header and a data cycle, the header cycle specifying the preset destination and source, and the data cycle being the first of the page table entry. And a page table entry removing apparatus specifying a mode address and a process identification. 12. The apparatus of claim 11 further comprising means for seating on said packet-switched bus by said first controller for a reply packet with said source. The apparatus of claim 12, wherein the first mode address and the second mode address are a virtual address and a physical address, respectively. 10. The apparatus of claim 9, wherein the request packet is transmitted via the packet switched bus to all other controllers coupled to the packet switched bus, wherein all other controllers are seated on the packet-switched bus for the predetermined destination. And a page table entry removing device. 15. The apparatus of claim 14, wherein the predetermined destination is indicated by all zeros in the request packet. ※ Note: The disclosure is based on the initial application.