JPH06282492A - Method and apparatus for removal of page table entry from plurality of address conversion buffers coupled to plurality of processors in multiprocessor system - Google Patents

Abstract

PURPOSE: To make it possible to remove the page table entry from the address conversion buffers ('TLB') coupled with the processors in the multiprocessor system. CONSTITUTION: This method consists roughly of a stage for sending a request packet so that the page table entry is removed from a 1st TLB 113, a stage for sending the request packet forward to a 2nd TLB 123 through a packet conversion path, a stage wherein the request packet specifies a specific source, a 1st address mode, and a process identifier, a stage for receiving the request packet on the packet conversion path by the 2nd TLB 123, a check stage for deciding wherein the 2nd TLB 123 decides whether or not the TLB itself contains the page table entry by comparing the 1st mode address with the process identifier, and a stage for removing the page table entry from the 2nd TLB 123 when the 2nd TLB 123 contains the page table entry.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the operation of virtual addressed memory in a multiprocessor computer system, and more particularly to an address translation buffer in such a system.

[0002]

BACKGROUND OF THE INVENTION In computer systems, it is very common for central processing units ("CPUs") to include cache memory to speed up memory access to main memory of the computer system. Although cache memory is small, it operates significantly faster than main memory. The cache memory is operably arranged between the CPU and main memory. During execution of software programs, cache memory stores the most frequently used instructions and data. Whenever the processor needs to access information from main memory,
The processor first examines the cache before accessing main memory. When the processor cannot find an instruction or data in the cache memory and a cache miss occurs, the slow main memory needs to be accessed. In this way, the CP by the cache memory
The average storage access time for U is reduced. cache·
For more information on memory, see John L. et al. Hennessy, David A. See Patterson, "Computer Architecture: Its Quantitative Approach" (Morgan, Kauffman Publishing, 1990).

In today's computer technology, the main memory ("physical memory") alone performs the processing, while the programmer or user feels that it is a much larger memory memory allocated to an external disk ( "Virtual storage"). Virtual storage enables highly efficient multiple programming, freeing the user from being unnecessarily tied to main storage. To provide virtual memory addressing, many processors translate a virtual memory virtual address into a physical memory physical address and a recently generated pair of virtual-physical addresses. And an address translation buffer (“TLB”) for caching. The TLB is important because main memory can be accessed quickly by skipping the mapping process if a pair of translated addresses already exists. A TLB entry is similar to a cache memory entry, where the tag holds a portion of the virtual address and the data portion is typically the physical page frame number, protected field, used bits, and dirty It holds bits and.

If the page mapping of the virtual-physical address of a given process is swapped out or slashed according to the needs of the process, the mapping needs to be discarded. Otherwise, the virtual address is reused by each process so the next process sending the virtual address can be terminated and the mapping obtained from the previous process. In computer systems with a single processor, a flush command is typically sent to the TLB to demap the target page.

However, in a multiprocessor computer system with shared storage, it is not possible to send individual flush commands to the processors because each processor along the system bus may have a copy of its page. It is an efficient task. It is possible to send an interrupt request to a processor, as is common in uniprocessor systems, but issuing an interrupt request to all processors controls the system bus and halts the execution of each processor operation. Means to do. Further, when the processor accepts the interrupt request, it issues the same flush command to each TLB, controls the system bus, and then
It needs to respond to the issuing processor. As each process becomes more complex and the number of processors increases, system-wide interrupts almost always appear. This is because each of the processors may perform jobs throughout the system and issue flush commands to all other processors.

[0006]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a broadcast page removal technique for all processors in a multiprocessor computer system.

It is a further object to provide a broadcast page removal technique for all processors without the penalties associated with sending and receiving interrupt requests in a multiprocessor computer system.

[0008]

In order to solve the above problems, in a multiprocessor system, a plurality of address translation buffers ("T
Method and apparatus for removing a page table entry from a "LB"). The method comprises sending a request packet by a first controller of the first TLB to remove the page table entry from the first TLB and identifying a predetermined source, the first address mode and a process identification. The second TLB in the request packet to
Sending the request packet to the packet conversion bus that is broadcast to a second control device coupled to the second control device; accepting the request packet on the packet conversion bus by the second control device; 2 control device is the first
Comparing the mode address with a process identifier to check to determine if the TLB contains the page table entry;
Completing the pending operation for the processor, the page table entry being the second TL.
If stored in B, removing the page table entry from the second TLB by the second controller, and sending a response packet to the first controller indicating completion by the second controller. And sending the response packet to the packet conversion bus that is forwarded to the first controller in a response packet identifying the source.

Notation and Terminology The following detailed description is based in large part on algorithms and symbolic representations of operations in computer systems. These algorithmic descriptions and representations are the means used by experts in the field of data processing to most effectively convey their work to other experts.

Algorithms are generally considered here to be a consistent, step-wise procedure leading to a desired result. These steps are those requiring physical manipulations of physical quantities. Without limitation, these physical quantities are usually in the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise processed. Presently, it has proven convenient to represent these signals in bits, numbers, elements, symbols, characters, terms, numbers, etc., primarily because they are commonly adopted.
However, it should be noted that all of these terms and similar terms are not associated with the appropriate physical quantities, but are merely convenient labels for these physical quantities.

Further, the processing performed is often referred to in terms, such as addition or comparison, associated with intelligent operations performed by human operators. In most cases, none of the above-disclosed operations forming part of the present invention will require or be desirable by a human operator. The operation is a machine operation. Machines useful for performing the operations of the present invention include general purpose digital computers or similar devices. It should always be noted that there is a distinction between the method of operation when operating a computer and the method of calculation itself. The present invention relates to method steps for operating a computer in processing electrical or other (eg mechanical, chemical) physical signals to produce another desired physical signal.

The present invention further relates to apparatus for performing these operations. This apparatus may be specially manufactured for the required purposes, or it may be a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. The algorithms disclosed herein are not inherently related to any particular computer or other apparatus. In particular, various general purpose machines can be utilized with programs written in accordance with the teachings herein. Alternatively, it may be more convenient to manufacture a more specialized device to carry out the necessary method steps. The required structure for a variety of these machines will appear from the description below.

Coding Description No specific programming language is presented to perform the various procedures disclosed herein. One of the reasons is that not all of the languages that can be mentioned are universally available. Each user of a particular computer is familiar with the language that best suits the purpose they face. In practice, it has been found useful to implement the invention in assembly language containing machine-executable target code. The detailed program listing is not provided because the computer and monitor systems that may be used in practicing the present invention are made up of many different elements.
The operations and other procedures described herein and illustrated in the accompanying drawings are disclosed to enable an expert to fully practice the invention.

[0014]

DETAILED DESCRIPTION A method and apparatus for deallocating memory translation pages in a multiprocessor computer system is disclosed. In the following description for purposes of explanation, specific memory, features, architectures, etc. are disclosed in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In another example, known circuits are shown in block diagram form in order not to unnecessarily obscure the present invention.

Referring now to FIG. 1, a multiprocessor
A simplified block diagram of a computer system is shown. Processor 110 is coupled to system bus 100 via cache controller 111 and bus watcher 112. The processor 110 further cooperates with the cache (not shown) of the virtual address already translated.
I / O to store the physical address mapping
An address translation buffer ("TLB") such as TLB 114 or system TLB 113 is used. Processors 120 and 130 similarly go through their respective cache controllers and bus watchers to system bus 10
Combined with 0. If the processor 110 needs to demap the virtual-to-physical address mapping of a single or multiple virtual pages, its cache controller 111 goes through the bus watcher 112 to the system bus 10.
Send a demap request packet to 0 by broadcast. When the other bus watchers 122 and 132 receive the demap request packet, these bus watchers execute the respective demapping request packet in order to execute the demap request packet.
The demap request packet is transferred to 21 and 131. After another cache controller completes its demapping, if there is a target page, cache controller 12
1 and 131 are respectively bus watchers 122 and 132
The bus watcher 11 of the processor 110 that has sent the demap request packet via
Notify 2 that demapping is complete in all other caches. The bus watcher 112 then sends a demap response to notify the processor 110 that sent the demap request packet that all other processors have completed processing.

In the present embodiment, the demap request packet consists of two cycles. In the header cycle, the address field is set to all zeros to indicate the broadcast packet, while the demapped components are identified in the data cycle as shown in FIG. The demap response packet acknowledges the previous demap request packet. This is currently two cycles long. The second cycle is not used and its content is "don't care". Internally, demap transactions are generated by the processor's memory flush operations. The information transferred for demapping includes the virtual address (“VFPA” 2
1) and Type 22 which are used as criteria for matching pages for removal within the TLB. Proces, commonly known as "context" in this field, used for demapping transactions
s_Id 20 is broadcast in bit 47 from 32 as shown in FIG. The lower 32 bits are equivalent to the flash operation data format.

In addition to broadcasting demap transactions over the system bus, the processor can accept external demaps. Referring to FIG.
The demap request from the processor 110 is received by the processor 12
When accepted by 0, the processor 120 performs the demapping as if the demapping request was internally generated, using the supplied process identifier rather than the current internal process identifier. Currently, the processor requires a single ready response for the demap operation. System hardware ensures that demap transactions are broadcast to and completed by all cache controllers in the system. Currently, the received demap utilizes a two phase request / response protocol. Only a single demap transaction is pending in the system at any one time to reduce the amount of state that must be held by the bus watcher.

Referring to FIG. 3, a timing diagram of a processor initiated demap transaction is illustrated. In this case, the demap transaction will be the full TLB in the multiprocessor system.
Utilized by the processor to remove page table entries from the. In this type of system,
The demap acts on the system TLB of the I / O TLB, other processors, or is simply reflected by the cache controller and no action is taken by that processor. The timing of demapping is similar to swap. That is, two responses are currently required. The first response uses WRDY_ to acknowledge acceptance of the demap request. The second response informs the processor that the demapping has completed successfully throughout the system. That signal is the RRDY_ signal. Both ready status signals WRDY_ and RRDY_ can be asserted simultaneously as shown in FIG. 3, but two separate ready responses need to be made. Exceptions can be reported to the demap by asserting an exception signal (not shown) with the RRDY_ response.

As shown in FIG. 3, the demap is Demap.
Communicated by asserting the bar and Address-Strobe bar signals. All information for demapping, including virtual address, process identifier and command information, is passed during the data cycle [63: 0]. This address is the "don't care" for demapping and is set to all zeros in the manner shown.

If there are systems associated with the processor that choose to take no action in response to the demap, then these systems must respond to the demap with two RRDY_ assertions. In this case, the cache controller will start RRDY in two consecutive cycles.
_ / WRDY_ can be held.

Referring now to FIG. 4, a timing diagram for an external demap request transaction is shown. If the demap is broadcast, the received demap is 2
Use the phase protocol. The first phase of this protocol is the external demap request 407. The second phase is the response 408 to this request. Another bus activity is allowed between request and response.

The phase portion of the demap request 407 is Adr.
ess-Strobe bar 400 and Demap-bar 4
Sent by the external bus master activating 01. The data cycle [63: 0] 402 must include a demap command 402 in the format shown in FIG. This command needs to be sent to the bus every single cycle. Currently, the processor is unable to respond to a request due to a pending operation that must be completed before responding to the demap request.

When the external request 407 has been processed internally, the processor initiates a demap response 408 transaction. This response 408 appears on the bus similar to an internally generated demap, but the major difference is that it is communicated as RD_403 rather than write. Note that WR_ does not change consistently.
This response is communicated by the processor asserting Address-Strobe bar 404 and Demap bar 405. R to complete the transaction
RDY_406 should be responded to by system logic.

[0024]

According to the above structure, the page removal broadcast communication technique can be provided for all processors without causing the disadvantages associated with the transmission and reception of interrupt requests.

[Brief description of drawings]

FIG. 1 is a simplified block diagram of a multiprocessor computer system.

FIG. 2 is a symbolic representation of a data cycle in a broadcast demap request.

FIG. 3 is a timing diagram of a processor-initiated demap transaction.

FIG. 4 is a timing diagram of an external demap request transaction.

[Explanation of symbols]

20 Process_ID 21 VFPA
(Virtual Address) 22 Type 100 System Bus 110 Processor 111 Cache Controller 112 Bus Watcher 113 System TLB (Address Translation Buffer) 114 I / O TLB 120 Processor 121 Cache Controller 122 Bus Watcher 123 TLB 130 Processor 131 Cache Controller 132 Bus Watcher 133 TLB

 ─────────────────────────────────────────────────── ─── Continued Front Page (71) Applicant 591174933 Xerox Corporation United States 06904-1600 Stanford Longridge Road, Connecticut 800 (72) Inventor Norman M. Hayes United States 94087 Sunnyvale, California Merrimack Drive 1121 (72) Inventor Pradeep Sindow United States 94040 California Mountain View Montalto Drive 1557 (72) Inventor Jean-Marc Frey Long United States 94306 California Palo Alto Pepper Avenue 408 (72) Inventor Sunil Nanda United States 94024 Los Altos, California Sandalwood Les IN 1225

Claims (3)

[Claims] 1. A multi-processor system in which data and command packets are transferred on a packet translation bus, removing page table entries from multiple address translation buffers ("TLBs") associated with multiple processors. In the above, each processor is a control device that controls reading and writing to the respective TLB, and the page table entry is an address mapping between the first mode address and the second mode address. And the page table entry is the first
Said method being of the form identified by mode address and process identification, wherein an invalid address mapping between said first address mode and said second address mode is performed in a first TLB coupled to a first processor. A page table entry containing the first TLB by the first controller of the first TLB.
A request packet to remove the page table entry from the device, and forwards the request packet specifying a predetermined source, the first address mode and process identification to a second controller associated with a second TLB. To the packet conversion bus for receiving the request packet on the packet conversion bus by the second controller, and by the second controller comparing the first mode address with a process identifier, The TLB
Checks to determine if it contains the page table entry, completes an ongoing operation for the second processor, and the page table entry is stored in the second TLB. Removes its page table entry from the second TLB by the second controller, issues a response packet by the second controller to indicate completion to the first controller, and identifies the source. Forwarding the response packet to the packet conversion bus for delivery to the first controller. 2. A circuit for removing one of a plurality of page table entries from a plurality of address translation buffers associated with a plurality of processors of a multiprocessor system having shared memory, each address translation A buffer stores a plurality of page table entries, the plurality of page table entries representing a mapping between virtual and physical addresses, each page table entry identified by its process identifier and virtual address. A packet conversion bus for transferring data and command packets to the plurality of processors of the multiplex microprocessor, and a data and command packet having corresponding processors as destinations on the packet conversion bus. Search for a given destination address Accepts the data and command packets, the first in the packet conversion bus and accepts the request
A receiver / receiver coupled to each processor and the packet translation bus for sending response packets, sending and receiving data and command packets, and a transceiver for each processor and a corresponding address translation buffer for address translation. A controller for reading and writing a buffer, wherein if the mapping between corresponding virtual addresses and physical addresses is not valid, the controller converts the plurality of address translations having the page table entry. A controller that sends a request packet to remove the page table entry from a buffer and the controller sends a response packet to the packet translation bus indicating that the removal of the page table entry is complete. A circuit characterized by that. 3. A page table entry is removed from a plurality of address translation buffers ("TLBs") associated with a plurality of processors in a multiprocessor system in which data and command packets are transferred on a packet translation bus. Device, where each processor has its own TL
A controller for controlling reading and writing to B, the page table entry representing an address mapping between a first mode address and a second mode address, the page table entry being the first mode thereof. A first T identified by an address and a process identification, said page table entry being associated with a first processor
An apparatus having an invalid address mapping between the first address mode and the second address mode in an LB, wherein the first TLB is controlled by a first controller of the first TLB.
Device for sending a request packet to remove the page table entry from a second source device, the request packet specifying a predetermined source, the first address mode and process identification to a second controller associated with a second TLB. A sending device for sending to the packet conversion bus for forwarding, a device for receiving the request packet on the packet conversion bus by the second control device, a first mode address coupled to the second control device, A comparing device for determining whether the TLB contains the page table entry by comparing with a process identifier; a device that completes pending operations for the second processor; By the second controller if a table entry is stored in the second TLB A device for removing the page table entry from the second TLB, a device for sending a response packet indicating completion by the second control device to the first control device, and a response packet for identifying the source for the first control packet. A device for sending to the packet conversion bus for transfer to a controller.