KR930021307A

KR930021307A - Arc prevention method by classification of discharge processing waveform

Info

Publication number: KR930021307A
Application number: KR1019920005521A
Authority: KR
Inventors: 서석용
Original assignee: 임창생; 재단법인 한국원자력연구소
Priority date: 1992-04-02
Filing date: 1992-04-02
Publication date: 1993-11-22
Also published as: KR950002091B1

Abstract

방전가공(electro discharge machining=EDM)시에 발생하는 전압 또는 전류파(voltage or current wave)의 파형을 분류하는 방법과 그 결과를 이용하여 아아크의 발생을 방지하는 방법에 관한 것으로서, 펄스형 방전가공시에는 발생하는 전압 또는 전류파형을, 회로열림(ON time) 초기에 발생하는 감시파(sampling pulse)의 고준위(high level)시에, 동전류파 최고치의 25내지 95퍼센트에 설정된 설정전위와 비교하여 설정치 이상인 신호로써 아아크에 일대일 상응하는 신호를 얻은후, 위 감시파를 시계(Clock)로 하여, 반전 플립플롭(flip flop)시켜, 방전시계(EDM clock)와 그리고(AND) 논리 결합한 신호를 방전전류 제어 반도체의 게이트 신호로 사용함으로써, 아아크 전류 흐름을 방지할수 있는 것을 특징으로 하는 논리회로로 구성됨을 특징으로 하는 “방전가공 파형의 분류에 의한 아아크 방지 방법”.The present invention relates to a method of classifying waveforms of voltage or current waves generated during electro discharge machining (EDM) and to preventing arc generation using the results. The voltage or current waveform generated at the time of comparison is compared with the set potential set at 25 to 95 percent of the maximum value of the electrokinetic wave at the high level of the sampling pulse generated at the beginning of the ON time. After acquiring a one-to-one correspondence to arc as a signal above the set value, use the clock as a clock, invert flip-flop, and discharge the signal combined with the EDM clock and the logic logic (AND). It is composed of a logic circuit characterized by preventing arc current flow by using it as a gate signal of a current control semiconductor. Prevention method ”.

Description

Arc prevention method by classification of discharge processing waveform

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 개략적인 방전파형을 도시한다. 도면 상반부는 방전전류파형을 나타내고, 하반부는 방전용 시계(EDI clock,본문참조)의 펄스를 나타낸다.1 shows a schematic discharge waveform. The upper half of the figure shows the discharge current waveform, and the lower half shows the pulse of the discharge clock (EDI clock).

제2도는 샘플링 펄스의 방전용 시계(EDI clock)에 대한 시간적위치를 도시한다. 항상 ON기간 개시초에 위치한다. 도면 상반부는 방전용 시계(EDM clock)를 나타내고, 하반부는 감시펄스를 나타낸다.2 shows the temporal position with respect to the EDI clock of the sampling pulse. It is always located at the beginning of the ON period. The upper half of the figure shows an EDM clock, and the lower half shows a monitoring pulse.

제3a도는 본원발명의 원리를 설명하는 논리표를 도시한다.Figure 3a shows a logic table illustrating the principles of the invention.

제3b도는 제3a도와 같다.FIG. 3B is the same as FIG. 3A.

제4a도는 일 실시예의 결과를 도시한다. 도면 상반부는 방전전류를 나타내고, 하반부는 감시펄스에 의한 아아크 발생 신호를 나타낸다.4A shows the results of one embodiment. The upper half of the figure shows the discharge current, and the lower half shows the arc generation signal by the monitoring pulse.

제4b도는 본원의 발명 효과중 일부를 도시한 것으로, 도면의 상반부는 방전전류를 나타내고, 하반부는 방전용 시계(EDM clock)를 도시한다.Figure 4b shows some of the effects of the present invention, the upper half of the figure shows the discharge current, the lower half shows the EDM clock.

Claims

The voltage or current waveform generated during pulsed discharge processing is set at 25 to 95 percent of the maximum value of the same current wave at the high level of the sampling pulse generated early in the circuit ON time. After acquiring a one-to-one correspondence to arc with a signal that is above the set potential compared to the set potential, the watchdog wave is clocked, inverted flip-flop, and the EDM clock and (AND) ) A logic circuit is constructed by using a logic-coupled signal as a gate signal of a discharge current control semiconductor to prevent arc or short-circuit current flow. ”.

The voltage or current waveform generated during pulsed discharge machining is compared with the set potential set at 25 to 95 percent of the peak of the same current wave at the high level of the sampling pulse that occurs early in the circuit ON time. Obtain a one-to-one correspondence to arc with a signal above the set value, and then trigger the gate of the down counter preset by the same signal, and then output the counter and the EDM clock and ( AND) A method of preventing arcing by classifying a discharge processing waveform, characterized in that a logic circuit is constructed which prevents arcing or short-circuit current flow by using a logic-coupled signal as a gate signal of a discharge current control semiconductor.

※ Note: The disclosure is based on the initial application.