KR930018687A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
KR930018687A
KR930018687A KR1019920001990A KR920001990A KR930018687A KR 930018687 A KR930018687 A KR 930018687A KR 1019920001990 A KR1019920001990 A KR 1019920001990A KR 920001990 A KR920001990 A KR 920001990A KR 930018687 A KR930018687 A KR 930018687A
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KR
South Korea
Prior art keywords
insulating film
source
etched
gate
forming
Prior art date
Application number
KR1019920001990A
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Korean (ko)
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KR100223795B1 (en
Inventor
허훈
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920001990A priority Critical patent/KR100223795B1/en
Publication of KR930018687A publication Critical patent/KR930018687A/en
Application granted granted Critical
Publication of KR100223795B1 publication Critical patent/KR100223795B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 종래의 제조방법에 있어서, 고집적 소자에 요구되는 디자인 룰과 단이 셀 면적감소로 인해 소오스와 드레인 정션간의 간격이 좁아져 숏채널효과를 억제할 수 없고 펀치쓰루현상이 야기되며 좁아지는 게이트 채널을 보상하기 위한 LDD 및 DDD구조를 형성하는 등의 복잡한 공정을 피하여 공정을 단순화 한 반도체 소자 제조방법에 관한 것으로 게이트를 형성하는 그위에 절연막과 소오스/드레인 콘택형 마스크를 형성하여 절연막을 경사에치 또는 습식식각하여 역원뿔형 및 역반구형 버퍼 절연막을 만들어 이온주입한 것이다.In the conventional manufacturing method, the gap between the source and the drain junction is narrowed due to the reduced cell area and the design rule required for the highly integrated device, so that the short channel effect cannot be suppressed and the punch-through phenomenon is caused. The present invention relates to a method of fabricating a semiconductor device that simplifies the process by avoiding complicated processes such as forming an LDD and a DDD structure to compensate the gate channel. An insulating film and a source / drain contact mask are formed on the gate to form an inclined layer. It is etched or wet etched to make an inverted conical and inverted hemispherical buffer insulating film and ion implanted.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 반도체 소자 공정단면도.2 is a cross-sectional view of a semiconductor device process of the present invention.

제3도는 본 발명 제2실시에의 반도체 소자 제조공정단면도.3 is a cross-sectional view of a semiconductor device manufacturing process according to the second embodiment of the present invention.

Claims (2)

기판에 게이트 및 게이트 측벽 절연막을 형성하는 공정과, 전면에 절연막을 증착하고 그위에 소오스/드레인 콘택형 마스크를 형성하는 공정과, 상기 마스크를 이용하여 상기 절연막을 경사에치하는 공정과, 상기 마스크를 제거하고 경사에칭된 상기 절연막을 마스크로 이용하여 이온주입으로 소오스/드레인 영역을 형성하는 공정으로 이루어짐을 특징으로 하는 반도체 소자 제조방법.Forming a gate and gate sidewall insulating film on a substrate, depositing an insulating film over the entire surface, and forming a source / drain contact mask thereon; using the mask to etch the insulating film diagonally; Removing the and forming a source / drain region by ion implantation using the inclined-etched insulating film as a mask. 제1항에 있어서, 절연막을 습식 식각하여 역반구형 버퍼 절연막으로 형성함을 특징으로 하는 반도체 소자 제조방법.The method of claim 1, wherein the insulating film is wet-etched to form a reverse hemispherical buffer insulating film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920001990A 1992-02-12 1992-02-12 Manufacturing method of semiconductor memory device KR100223795B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920001990A KR100223795B1 (en) 1992-02-12 1992-02-12 Manufacturing method of semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920001990A KR100223795B1 (en) 1992-02-12 1992-02-12 Manufacturing method of semiconductor memory device

Publications (2)

Publication Number Publication Date
KR930018687A true KR930018687A (en) 1993-09-22
KR100223795B1 KR100223795B1 (en) 1999-10-15

Family

ID=19328839

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920001990A KR100223795B1 (en) 1992-02-12 1992-02-12 Manufacturing method of semiconductor memory device

Country Status (1)

Country Link
KR (1) KR100223795B1 (en)

Also Published As

Publication number Publication date
KR100223795B1 (en) 1999-10-15

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