KR930015666A - Synchronous Signal Processing Device in Image System - Google Patents
Synchronous Signal Processing Device in Image System Download PDFInfo
- Publication number
- KR930015666A KR930015666A KR1019910023342A KR910023342A KR930015666A KR 930015666 A KR930015666 A KR 930015666A KR 1019910023342 A KR1019910023342 A KR 1019910023342A KR 910023342 A KR910023342 A KR 910023342A KR 930015666 A KR930015666 A KR 930015666A
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- reference voltage
- frequency
- oscillation
- synchronization
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Synchronizing For Television (AREA)
Abstract
본 발명의 동기신호 처리장치는, 동기 분리회로와 자동주파수 조정회로 및 발진회로외에, 상기 동기분리 신호로부터 출력되는 동기신호의 주파수를 감지하는 주파수 감지회로와, 상기 주파수 감지회로의 출력에 따라 소정레벨의 기준전압을 상기 자동주파수 조정회로로 공급하는 기준전압 회로와, 상기 기준전압 회로에 의하여 제어되고 상기 발진회로의 발진신호에 따라 소정의 영상패턴 신호를 출력하는 패턴발생회로를 더 가진다.The synchronization signal processing apparatus of the present invention includes a frequency sensing circuit for sensing the frequency of the synchronization signal output from the synchronization separation signal, in addition to the synchronization separation circuit, the automatic frequency adjustment circuit, and the oscillation circuit, and according to the output of the frequency detection circuit. A reference voltage circuit for supplying a reference voltage of a level to the automatic frequency adjustment circuit, and a pattern generating circuit controlled by the reference voltage circuit and outputting a predetermined image pattern signal according to the oscillation signal of the oscillation circuit.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 종래의 동기신호 처리장치의 블럭다이어그램, 제2도는 본 발명의 동기신호 처리장치의 블럭다이어그램.1 is a block diagram of a conventional synchronous signal processing apparatus, and FIG. 2 is a block diagram of a synchronous signal processing apparatus according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910023342A KR950006355B1 (en) | 1991-12-18 | 1991-12-18 | Synchronizing signal processing unit for composite image system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019910023342A KR950006355B1 (en) | 1991-12-18 | 1991-12-18 | Synchronizing signal processing unit for composite image system |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930015666A true KR930015666A (en) | 1993-07-24 |
KR950006355B1 KR950006355B1 (en) | 1995-06-14 |
Family
ID=19325116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910023342A KR950006355B1 (en) | 1991-12-18 | 1991-12-18 | Synchronizing signal processing unit for composite image system |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950006355B1 (en) |
-
1991
- 1991-12-18 KR KR1019910023342A patent/KR950006355B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR950006355B1 (en) | 1995-06-14 |
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E701 | Decision to grant or registration of patent right | ||
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Payment date: 20070514 Year of fee payment: 13 |
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LAPS | Lapse due to unpaid annual fee |