KR930014066A

KR930014066A - Sending / receiving data processing method using FIFO

Info

Publication number: KR930014066A
Application number: KR1019910026021A
Authority: KR
Inventors: 황정우
Original assignee: 정몽헌; 현대전자 산업 주식회사
Priority date: 1991-12-31
Filing date: 1991-12-31
Publication date: 1993-07-22

Abstract

본 발명은 FIFO를 사용하는 회로에서 FIFO의 괸 단자로 나와 있는 다수의 플랙을 이용하여 제어신호를 발생시켜 FIFO를 고속으로 사용하기에 적당하도록 한 FIFO를 이용한 송수신 데이타 처리방법에 관한 것으로 리드와 라이트를 동시에 수행할 수 있음은 물론 메모리를 억세스 할때와 같은 복잡한 어드레스 버스가 필요없는 장점을 가진 FIFO를 이용하되 송신축의 정지 및 스타트 시그널 사이에 플립플롭(FF₁)과 앤드게이트(A₁) 및 인버터(I₁)(I₂)를 구비하고 수신측의 정지시그널과스타트 시그널 사이에 플립플롭(FF₂)과 앤드 게이트(A₂) 및 인버티(I₃)를 구비하여 송신측, 수신측 모두 상대방의 속도에 관계없이 데이타를 고속으로 전송할 수 있게 한 것이다.The present invention relates to a transmission and reception data processing method using a FIFO to generate a control signal using a plurality of flags appearing in the 괸 terminal of the FIFO in a circuit using the FIFO so that the FIFO is suitable for high speed use. The FIFO has the advantage that it can simultaneously perform the process and eliminates the need for complicated address buses such as accessing memory, but the flip-flop (FF ₁ ) and the end gate (A ₁ ) between the stop and start signals of the transmission axis. And an inverter (I ₁ ) (I ₂ ) and a flip-flop (FF ₂ ), an end gate (A ₂ ), and an inverting (I ₃ ) between the stop signal and the start signal on the receiving side. Both sides are able to transmit data at high speed regardless of the speed of the other side.

Description

Sending / receiving data processing method using FIFO

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

제2도는 본 발명 송신측에서의 라이트 흐름도.2 is a light flow diagram at the transmitting side of the present invention.

제3도는 본 발명 수신측에서의 리드 흐름도.3 is a lead flow chart at the receiving side of the present invention.

Claims

If the sending side writes faster than the receiving side third speed, the full-flag is set and this signal is sent to the transmitting side to stop the data transmission from the transmission axis, and the receiving side signals more than half of the data filled in the FIFO. Means for transmitting to the transmitting side to start writing to the FIFO at the transmitting side, and when the receiving side reads faster than the transmitting side writes, the amplifier flag Ef is counted and the signal is sent to the receiving side. And a means for stopping a data read from the memory and transmitting a start signal to the receiving side when the transmitting side rides in at least half the memory of the FIFO to start the reading in the FIFO.

※ Note: The disclosure is based on the initial application.