KR930012117B1 - Method of fabricating a rough surface poly-si growth by solid phase crystallization - Google Patents
Method of fabricating a rough surface poly-si growth by solid phase crystallization Download PDFInfo
- Publication number
- KR930012117B1 KR930012117B1 KR1019910010016A KR910010016A KR930012117B1 KR 930012117 B1 KR930012117 B1 KR 930012117B1 KR 1019910010016 A KR1019910010016 A KR 1019910010016A KR 910010016 A KR910010016 A KR 910010016A KR 930012117 B1 KR930012117 B1 KR 930012117B1
- Authority
- KR
- South Korea
- Prior art keywords
- silicon layer
- temperature
- silicon
- deposited
- heat treatment
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 공지된 기술로 실리콘층을 증착한 것을 SEM 장비로 촬영한 사진.1 is a photograph taken with a SEM device to deposit a silicon layer by a known technique.
제2도는 제1도의 실리콘층을 본 발명에 의해 열처리한 상태를 SEM 장비로 촬영한 사진.Figure 2 is a photograph taken with SEM equipment the state that the heat treatment of the silicon layer of Figure 1 according to the present invention.
제3a도는 내지 제3c도는 실리콘층을 본 발명에 의해 열처리하되 열처리 시간을 다르게한 상태를 SEM 장비로 촬영한 사진.Figure 3a to Figure 3c is a photograph taken by SEM equipment in a state that the heat treatment of the silicon layer in accordance with the present invention, but the heat treatment time is different.
제4도는 LPCVD의 증착반응기의 석영관과 석영관 내부에 장착되는 웨이퍼 위치를 도시한 도면.4 shows the position of a wafer mounted inside a quartz tube and a quartz tube of an LPCVD deposition reactor.
제4a도는 내지 제4f도는 석영관내의 장착된 웨이퍼 상부에 예정된 온도에서 실리콘층을 증착한 후, 각각의 웨이퍼 상부의 실리콘층을 SEM 장비로 촬영한 사진.Figures 4a to 4f is a photograph of the silicon layer on each wafer after depositing the silicon layer at a predetermined temperature on the mounted wafer in the quartz tube, SEM photograph.
제5a도는 내지 제5e도는 제4a도 내지 제4f도의 증착된 실리콘층을 본 발명의 열처리 공정을 거친후 SEM 장비로 촬영한 사진.5a to 5e is a photograph taken with the SEM equipment after the deposited silicon layer of FIGS. 4a to 4f through the heat treatment process of the present invention.
본 발명은 고집적 반도체 소자의 표면적이 증대된 전하저장전극 제조방법에 관한 것으로, 특히 전하저장전극의 표면에 반구형태를 갖도록 하여 표면적을 증대시킨 전하저장전극 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a charge storage electrode having an increased surface area of a highly integrated semiconductor device, and more particularly, to a method of manufacturing a charge storage electrode having a hemispherical shape on the surface of the charge storage electrode to increase its surface area.
일반적으로 사용되고 있는 DRAM은 하나의 트랜지스터와 하나의 캐패시터가 접속된 구성으로 되어 있으며, 캐패시터 전극으로 불순물이 주입된 다결정 실리콘층을 사용하고 있다. 이때 캐패시터의 용량은 전극으로 사용되는 실리콘층의 면적과 유전체막의 유전율과 두께에 의해 정해지는데, 적극으로 사용되는 실리콘층의 표면적이 클수록 캐패시터 형성시 큰 충전용량을 얻을 수 있어 안정된 DRAM 셀을 얻을 수 있고, 캐패시터가 차지하는 면적을 최소화할 수 있다.A DRAM generally used has a structure in which one transistor and one capacitor are connected, and a polycrystalline silicon layer in which impurities are injected into a capacitor electrode is used. At this time, the capacitance of the capacitor is determined by the area of the silicon layer used as the electrode and the dielectric constant and thickness of the dielectric film. The larger the surface area of the silicon layer used as the electrode, the larger the charge capacity can be obtained when the capacitor is formed, thereby obtaining a stable DRAM cell. And the area occupied by the capacitor can be minimized.
전하저장전극의 표면적을 증대시키는 방법은 여러 가지가 있으나, 이하에서는 전하저장전극의 표면에 반구형태의 구조를 갖도록 하는 제조방법에 대하여 언급하고자 한다.Although there are various methods for increasing the surface area of the charge storage electrode, the following will describe a manufacturing method for having a hemispherical structure on the surface of the charge storage electrode.
종래 기술의 한예는 특정의 온도(예를 들어 550℃)에서 LPCVD(Low Pressure Chemical Vapor Deposition) 방법으로 실리콘층을 증착하여 실리콘층의 표면에 반구형상(hemispherical grains)을 만들어서 동일면적에서 표면적을 두배정도 증대시켰는데 이 방법은 증착조건이 온도와 압력에 크게 민감하여 런과 런간(Run-to-Run), 웨이퍼와 웨이퍼간(wafer-to-wafer), 웨이퍼내부(within-wafer)에서 면적증가의 편차가 커서 실제 생산에는 적용하기가 부적합하다.One example of the prior art is to deposit a silicon layer by LPCVD (Low Pressure Chemical Vapor Deposition) at a specific temperature (e.g. 550 ° C) to create hemispherical grains on the surface of the silicon layer, thus doubling the surface area at the same area. In this method, the deposition conditions are very sensitive to temperature and pressure, which increases the area in run and run-to-run, wafer-to-wafer, and with-wafer. Because of its large deviation, it is not suitable for actual production.
또한, 종래기술의 또 다른예는 실리콘 증착단계에서는 LPCVD 방법으로 실리콘층을 증착하여 평탄한 구조를 형성하고, 후속공정으로 예를들어 60℃ 이상의 온도와 고진공(예를들어 10-6torr이하)상태에서 실리콘층을 열처리하여 실리콘층을 표면에 반구형상을 형성하였다.In addition, another example of the prior art is to deposit a silicon layer by the LPCVD method in the silicon deposition step to form a flat structure, and in a subsequent process, for example, a temperature of more than 60 ℃ and high vacuum (for example 10 -6 torr or less) The silicon layer was heat-treated at to form a hemispherical shape on the surface of the silicon layer.
그러나, 이 방법은 현재 사용하는 증착반응로의 석영관에서 10-6torr 이하의 고진공으로 유지하는 것은 매우 위험한 일이므로 새로운 장비가 필요하게 되며 실리콘 증착후 증착반응기의 압력을 고진공으로 변환시키는데 약 12시간 정도가 소요되어 생산성이 떨어진다.However, this method is very dangerous to maintain a high vacuum of 10 -6 torr or less in the quartz tube of the current deposition reactor. Therefore, new equipment is needed and it is necessary to convert the pressure of the deposition reactor into a high vacuum after deposition. It takes time and productivity decreases.
따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위하여 증착 단계에서 평탄한 구조를 형성한 다음, 증착반응로 내부의 온도는 600℃ 이상, 입력은 저진공인 상태에서 열처리하여 반구형상을 얻을 수 있는 표면적이 증대된 전하저장전극 제조방법을 제공하는데 그 목적이 있다.Therefore, the present invention forms a flat structure in the deposition step in order to solve the problems of the prior art, and then heat treatment in a state in which the temperature inside the deposition reactor is higher than 600 ℃, the input is low vacuum to obtain a hemispherical shape It is an object of the present invention to provide a method for manufacturing a charge storage electrode having an increased surface area.
본 발명에 의하면 전하저장 전극용 실리콘층을 LPCVD 방법으로 비정질 실리콘에서 다결정 실리콘으로 천이되는 온도보다 낮은 온도에서 예정된 두께 증착한 다음, 반응기 튜브내에 불활성 기체를 채우고, 압력은 수십-수백 mtorr, 온도는 600℃ 이상의 조건에서 예정된 시간동안 상기 증착된 실리콘층을 열처리하여. 그로인하여 실리콘층 표면이 반구형상을 갖도록 하는 것을 특징으로 한다.According to the present invention, the silicon layer for charge storage electrode is deposited by a predetermined thickness at a temperature lower than the temperature transitioned from amorphous silicon to polycrystalline silicon by LPCVD method, and then filled with an inert gas in the reactor tube, and the pressure is several tens to several hundred mtorr, and the temperature is Heat-treating the deposited silicon layer for a predetermined time at a temperature of 600 ° C. or higher. Therefore, the surface of the silicon layer is characterized by having a hemispherical shape.
이하 첨부된 도면을 참고하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1도는 공지된 기술로 실리콘층을 증착한 것을 SEM 장비로 촬영한 사진으로서, SiH4, Si2H6또는 Si 소스가 포함된 기체를 사용하여 LPCVD 방법으로 비정질 실리콘에 다결정 실리콘으로 천이되는 온도보다 낮은 온도인 550~580℃에서 실리콘층을 예정된 두께로 증착한 것이다.FIG. 1 is a SEM photograph of a deposition of a silicon layer using a known technique. The temperature of transition of amorphous silicon to polycrystalline silicon by LPCVD using a gas containing SiH 4 , Si 2 H 6, or a Si source. At a lower temperature, 550-580 ° C, the silicon layer was deposited to a predetermined thickness.
제2도는 본 발명에 의해 제1도에서 증착된 실리콘층을 공기중에 노출시키지 않는 인-시투(in-Situ) 공정으로 반응기 튜브내의 조건, 예를 들어 불활성기체 분위기(Nz,Ar,He)를 채우고, 압력은 수십~수백 mtorr, 600℃ 이상의 온도에서 예정된 시간 열처리(Anneal)하여 실리콘층 표면이 반구형태로 변화시킨 것을 SEM 장비로 촬영한 사진이다.FIG. 2 is an in-situ process which does not expose the silicon layer deposited in FIG. 1 to air in accordance with the present invention, for example in an inert gas atmosphere (Nz, Ar, He). Filled, the pressure is a photograph taken by SEM equipment that the surface of the silicon layer is changed to hemispherical shape by annealing for a predetermined time at a temperature of tens to hundreds of mtorr, 600 ℃ or more.
제3a도는 제2도에 도시한 바와같이 반응기내의 튜브조건에서 1시간 열처리하였을 때, 제3b도는 상기와 같은 조건에서 6시간 열처리하였을 때, 제3c도는 상기와 같은 조건에서 12시간을 열처리하였을때를 각각 SEM 장비로 촬영한 사진으로서, 열처리하는 시간을 증가시킬수록 실리콘층의 표면에 형성되는 반구들의 입자 크기가 증대되는 것을 알 수 있다.FIG. 3a shows the heat treatment for 1 hour at the tube conditions in the reactor as shown in FIG. 2, FIG. 3b shows the heat treatment for 6 hours under the above conditions, and FIG. 3c shows the heat treatment for 12 hours under the same conditions. As taken by SEM equipment, it can be seen that the particle size of the hemispheres formed on the surface of the silicon layer increases as the time for heat treatment is increased.
제4도는 LPCVD의 증착반응기의 석영관(10)과 석영관(10)내부에 장착되는 웨이퍼의 위치(1~5)를 도시한 단면도로서, 웨이퍼가 석영관의 중심에서 좌,우로 배열됨을 알 수 있다.FIG. 4 is a cross-sectional view showing the positions (1 to 5) of the quartz tube 10 and the wafers mounted inside the quartz tube 10 of the deposition reactor of LPCVD, showing that the wafers are arranged left and right from the center of the quartz tube. Can be.
제4a도 내지 제4f도는 제4도의 석영관(10)내부에 웨이퍼를 1~5위치에 각각 장착하고, 예정된 온도에서 실리콘층을 증착하고, 실리콘층 표면을 SEM 장비로 촬영한 사진으로서, 각각의 위치에 따라 실리콘층 표면현상이 다르다는 것을 알 수 있다. 이것은 석영관내의 온도편차에 의해 발생되는 것으로서, 각각의 웨이퍼 위치마다 실리콘층의 표면형상에 상당한 차이가 있으므로 실제 생산에 적용하는데 큰 문제가 된다.4A to 4F show wafers mounted at positions 1 to 5 in the quartz tube 10 of FIG. 4, respectively, and depositing a silicon layer at a predetermined temperature, and photographing the surface of the silicon layer with SEM equipment. It can be seen that the surface phenomenon of the silicon layer is different depending on the position of. This is caused by the temperature deviation in the quartz tube, and there is a significant difference in the surface shape of the silicon layer at each wafer position, which is a great problem for practical production.
그러나, 제5a도 내지 제5e도는 상기의 제4a도 내지 제4f도와 같이 실리콘층을 증착한 다음, 본 발명에 의해 열처리 공정을 진행한 것을 SEM 장비로 촬영한 사진으로서, 석영관내의 웨이퍼위치(1~5)와 관계없이 실리콘층의 표면에 표면적이 증대된 반구형상이 거의 균일하게 형성됨을 도시한다.However, FIGS. 5A to 5E are SEM photographs of the silicon layer deposited as shown in FIGS. 4A to 4F and then subjected to the heat treatment process according to the present invention. Irrespective of 1 to 5), it is shown that a hemispherical shape with an increased surface area is formed almost uniformly on the surface of the silicon layer.
상기한 바와같이 본 발명에 의하면 저진공(수십~수백torr)에서 열처리를 실시함으로 고진공 열처리에 사용될 수 있는 새로운 장비가 필요하지 않고, 실리콘증착 반응기내에서 인-시투 공정으로 열처리하는 동시에 고진공 상태로 만드는 시간이 필요하지 않아 생산성을 향상시킬 수 있으며, 종래기술에 비교하여 런-to-런, 웨이퍼-to-웨이퍼, 웨이퍼 내부에서 재현성이 있는 표면적이 증대된 균일한 반구형상을 얻을 수 있다.As described above, according to the present invention, heat treatment is carried out at low vacuum (several to hundreds of torr), so that no new equipment that can be used for high vacuum heat treatment is required, and at the same time, heat treatment is performed in an in-situ process in a silicon deposition reactor. The production time is not required, so productivity can be improved, and a uniform hemispherical shape with increased reproducible surface area inside the run-to-run, wafer-to-wafer, and wafer can be obtained compared to the prior art.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910010016A KR930012117B1 (en) | 1991-06-15 | 1991-06-15 | Method of fabricating a rough surface poly-si growth by solid phase crystallization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910010016A KR930012117B1 (en) | 1991-06-15 | 1991-06-15 | Method of fabricating a rough surface poly-si growth by solid phase crystallization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930001433A KR930001433A (en) | 1993-01-16 |
| KR930012117B1 true KR930012117B1 (en) | 1993-12-24 |
Family
ID=19315909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910010016A KR930012117B1 (en) | 1991-06-15 | 1991-06-15 | Method of fabricating a rough surface poly-si growth by solid phase crystallization |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930012117B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100238205B1 (en) * | 1996-10-05 | 2000-01-15 | 윤종용 | Fabrication Method for Polysilicon layer having HSG-Si thereon |
| KR101010924B1 (en) * | 2008-07-01 | 2011-01-25 | 연세대학교 산학협력단 | Focused ion beam apparatus using opening feature and machining method using thereof |
-
1991
- 1991-06-15 KR KR1019910010016A patent/KR930012117B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930001433A (en) | 1993-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0521644B1 (en) | Method of manufacturing polysilicon film | |
| US5634974A (en) | Method for forming hemispherical grained silicon | |
| US5344796A (en) | Method for making polycrystalline silicon thin film | |
| US7238613B2 (en) | Diffusion-enhanced crystallization of amorphous materials to improve surface roughness | |
| US4529621A (en) | Process for depositing a thin-film layer of magnetic material onto an insulative dielectric layer of a semiconductor substrate | |
| JPH0714797A (en) | Uniform doping of hemispherical granulal surface polycrystaline silicon | |
| JP2001510945A (en) | Hemispherical granular polysilicon semiconductor structure and method of manufacturing the same | |
| KR100247931B1 (en) | Method for manufacturing semiconductor device having hsg-si layer | |
| KR100299784B1 (en) | A method for forming a textured polysilicon layer, a substrate processing apparatus used to implement this method, and a semiconductor memory device | |
| US4341818A (en) | Method for producing silicon dioxide/polycrystalline silicon interfaces | |
| KR100234380B1 (en) | Manufacturing method of semiconductor device having hsg-si layer | |
| KR930012117B1 (en) | Method of fabricating a rough surface poly-si growth by solid phase crystallization | |
| KR100364036B1 (en) | Method of manufacturing a semiconductor device and a semiconductor device | |
| EP0941552B1 (en) | Semiconductor device with memory capacitor and method of manufacturing such a device | |
| US5382549A (en) | Method of manufacturing polycrystalline silicon having columnar orientation | |
| JP2861343B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH04280669A (en) | Forming method of polycrystalline silicon film | |
| JP2882217B2 (en) | Method for manufacturing semiconductor device | |
| JP2910422B2 (en) | Method for manufacturing semiconductor device | |
| KR100255662B1 (en) | Method for manufacturing semiconductor device having polysilicon layer of hemisphere grain | |
| JP3034377B2 (en) | Method for manufacturing capacitor electrode in semiconductor device | |
| JPH03126220A (en) | Semiconductor element | |
| JP2004193573A (en) | Manufacturing method of capacitor | |
| US6083833A (en) | Method for forming conductive film for semiconductor device | |
| JPH021124A (en) | Manufacture of dielectric film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20091126 Year of fee payment: 17 |
|
| LAPS | Lapse due to unpaid annual fee |