KR930011459B1 - Isolation method of semiconductor - Google Patents

Isolation method of semiconductor Download PDF

Info

Publication number
KR930011459B1
KR930011459B1 KR1019910000562A KR910000562A KR930011459B1 KR 930011459 B1 KR930011459 B1 KR 930011459B1 KR 1019910000562 A KR1019910000562 A KR 1019910000562A KR 910000562 A KR910000562 A KR 910000562A KR 930011459 B1 KR930011459 B1 KR 930011459B1
Authority
KR
South Korea
Prior art keywords
oxide film
depositing
film
silicon
silicon nitride
Prior art date
Application number
KR1019910000562A
Other languages
Korean (ko)
Other versions
KR920015510A (en
Inventor
김충현
Original Assignee
금성일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성일렉트론 주식회사, 문정환 filed Critical 금성일렉트론 주식회사
Priority to KR1019910000562A priority Critical patent/KR930011459B1/en
Publication of KR920015510A publication Critical patent/KR920015510A/en
Application granted granted Critical
Publication of KR930011459B1 publication Critical patent/KR930011459B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Abstract

A semiconductor device is prepared by depositing and etching a 1st oxide film on a substrate, depositing polycrystalline silicon to form a single crystalline film of polycrystalline silicon, depositing a 2nd oxide film thereon, patterning it, etching the single crystalline silicon, depositing a silicon nitride film, forming side walls thereon by RIE process, forming a partial oxide film, removing the silicon nitride film and the 2nd oxide film in order. The device has a complete isolation of the oxide film and few parasite capacitance.

Description

반도체 소자의 격리방법Isolation Method of Semiconductor Devices

제1도는 본 발명의 공정단면도.1 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : 제1산화막1 substrate 2 first oxide film

3 : 다결정실리콘 4 : 단결정화된 실리콘3: polycrystalline silicon 4: monocrystalline silicon

5 : 제2산화막 6 : 포토리지스트5: second oxide film 6: photoresist

7 : 국부산화막7: local oxide film

본 발명은 반도체 소자의 격리방법에 관한 것으로, 특히 고집적 미세회로의 소프트-에러(Soft-error)면역성을 증대시킴은 물론 고속 동작의 소자를 얻기에 적당하도록 한 것이다.The present invention relates to a method for isolating semiconductor devices, and in particular, to increase the soft-error immunity of highly integrated microcircuits, as well as to obtain a device of high speed operation.

종래의 소자 격리 방법에는 국부산화방법(Local Oxidation), 프리-국부방법(전체적으로 절연막을 성장시키거나 증착하는 방법), 트랜치 방법등이 있으나 고신뢰성 및 고속동작 소자 제조시 사용되는 완전 산화막 소자 격리 기술 사용시 완전한 단결정 기판을 얻을 수 없어 소자 특성에 많은 제약이 있다.Conventional device isolation methods include local oxidation method, pre-local method (to grow or deposit an insulating film as a whole), trench method, etc., but a complete oxide device isolation technology used in manufacturing high reliability and high speed operation devices. In use, it is impossible to obtain a complete single crystal substrate, and there are many restrictions on device characteristics.

본 발명은 상기와 같은 종래의 결점을 해결하기 위한 것으로 기판의 완전한 단결정이 형성되지 않아 소자특성이 저하되는 것을 방지하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to prevent deterioration of device characteristics because a single crystal of a substrate is not formed.

이하에서 이와같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면 제1도에 의하여 상술하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving such an object will be described in detail with reference to the accompanying drawings of FIG. 1.

먼저(A)와 같은 실리콘기판(1)위에 제1산화막(2)을 성장시키고, (B)와 같이 제1산화막(2)을 선택적식각한 후 다결정실리콘(3)을 형성하고 이를 단결정화(Recrystallization) 시킨다.First, the first oxide film 2 is grown on the silicon substrate 1 as shown in (A), and the first oxide film 2 is selectively etched as shown in (B), and then polycrystalline silicon 3 is formed and monocrystallized ( Recrystallization).

그리고 (C)와 같이 단결정화된 실리콘(4)위에 제2산화막(5)을 성장시키고 포토리지스트(6)를 도포하여 선택적 식각한다.As shown in (C), the second oxide film 5 is grown on the single crystallized silicon 4, and the photoresist 6 is applied to selectively etch it.

다음에 (D)와 같이 제2산화막(5)을 식각하고 포토리지스트(6)를 제거한 후 (E)와 같이 단결정화된 실리콘(4)을 식각한다. 이어서 (F)와 같이 실리콘질화막(6)을 증착하고 (G)와 같이 실리콘질화막(6)을 RIE 공정으로 에치함으로 측벽을 형성한다.Next, as shown in (D), the second oxide film 5 is etched, the photoresist 6 is removed, and the single crystallized silicon 4 is etched as shown in (E). Subsequently, the silicon nitride film 6 is deposited as shown in (F), and the sidewalls are formed by etching the silicon nitride film 6 as shown in (G) by the RIE process.

다음에 (H)와 같이 국부산화막(7)을 형성하고 (I)와 같이 실리콘질화막(6)을 제거한 후 (J)와 같이 제2산화막(5)을 제거한다.Next, the local oxide film 7 is formed as shown in (H), the silicon nitride film 6 is removed as shown in (I), and the second oxide film 5 is removed as shown in (J).

이상과 같은 본 발명에 의하면 완전 산화막 격리에 의한 고신뢰성의 소자를 제조할 수 있으며, 기생 커패시턴스의 감소로 인한 고속 동작의 소자를 제조할 수 있고, 다층구조 소자제조에 직접 적용가능한 장점이 있다.According to the present invention as described above it is possible to manufacture a highly reliable device by the complete oxide film isolation, it is possible to manufacture a device of a high speed operation due to the reduction of parasitic capacitance, there is an advantage that can be directly applied to the manufacture of a multi-layered device.

Claims (1)

기판위에 제1산화막을 성장시키고 식각한 후 다결정 실리콘을 증착하여 다결정 실리콘의 단결정화를 이루는 공정과, 상기 단결정화된 실리콘에 제2산화막을 성장시키고 이 제2산화막을 패터닝한 후 단결정화된 실리콘을 에치하는 공정과, 실리콘질화막을 증착하고 이 실리콘질화막에 RIE 공정을 실시하여 측벽을 형성하는 공정과, 국부산화막을 형성하고 상기 실리콘질화막을 제거한 후 상기 제2산화막을 제거하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 반도체 소자의 격리방법.Growing and etching a first oxide film on a substrate and depositing polycrystalline silicon to form a single crystal of polycrystalline silicon; The step of etching the silicon nitride film, the step of depositing a silicon nitride film and performing a RIE process on the silicon nitride film to form a sidewall, and forming a local oxide film, removing the silicon nitride film, and then removing the second oxide film Isolation method of a semiconductor device, characterized in that made by.
KR1019910000562A 1991-01-15 1991-01-15 Isolation method of semiconductor KR930011459B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000562A KR930011459B1 (en) 1991-01-15 1991-01-15 Isolation method of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000562A KR930011459B1 (en) 1991-01-15 1991-01-15 Isolation method of semiconductor

Publications (2)

Publication Number Publication Date
KR920015510A KR920015510A (en) 1992-08-27
KR930011459B1 true KR930011459B1 (en) 1993-12-08

Family

ID=19309829

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000562A KR930011459B1 (en) 1991-01-15 1991-01-15 Isolation method of semiconductor

Country Status (1)

Country Link
KR (1) KR930011459B1 (en)

Also Published As

Publication number Publication date
KR920015510A (en) 1992-08-27

Similar Documents

Publication Publication Date Title
US6174784B1 (en) Technique for producing small islands of silicon on insulator
US4507158A (en) Trench isolated transistors in semiconductor films
KR920010132B1 (en) Manufacturing method of hetero-epitaxial layer usidetermination of potassium ions in fluids ng re-growing process
US5073516A (en) Selective epitaxial growth process flow for semiconductor technologies
US5185286A (en) Process for producing laminated semiconductor substrate
KR890003382B1 (en) Manufacturing method of dielectronic isolation complementary ic.
JP2006529055A (en) Thermal history solution
US5061653A (en) Trench isolation process
JP2785918B2 (en) Method of manufacturing semiconductor device having growth layer on insulating layer
KR970013188A (en) Device isolation method of semiconductor device
US5548154A (en) Isoplanar isolated active regions
KR930011459B1 (en) Isolation method of semiconductor
KR890003146B1 (en) Manufacture of semiconductor device
JP2690412B2 (en) Method of manufacturing semiconductor device having growth layer on insulating layer
US5208167A (en) Method for producing SOI substrate
KR100209714B1 (en) Isolation film of semiconductor device and method for forming the same
JPS6047239B2 (en) Method for manufacturing single crystal silicon thin film
KR940005737B1 (en) Manufacturing method of soi semiconductor device
US4353159A (en) Method of forming self-aligned contact in semiconductor devices
KR0124482B1 (en) Forming method of isolation oxide film in semiconductor device
JP2793460B2 (en) Manufacturing method of SOI structure
KR100334390B1 (en) Manufacturing method for dual gate oxide
KR100416813B1 (en) Field Oxide Formation Method of Semiconductor Device
KR950003900B1 (en) Semiconductor device manufacturing method for soi structure
KR100253268B1 (en) Semiconductor element isolation method

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20051118

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee