KR930011442A

KR930011442A - Direct Digital Synthesis Method and Circuit Using Phase Accumulator

Info

Publication number: KR930011442A
Application number: KR1019910021256A
Authority: KR
Inventors: 조인제
Original assignee: 정용문; 삼성전자 주식회사
Priority date: 1991-11-26
Filing date: 1991-11-26
Publication date: 1993-06-24

Abstract

디지탈 합성회로에 있어서, 고정주파수 클럭신호와 디지탈 등조워드를 입력하여 매 클럭주기마다 사인파의 현재 위상에 대응하는 위상정보를 발생하고, 상기 위상축적기의 출력 위상정보에 따라 진폭 정보신호를 발생한다.In a digital synthesis circuit, a fixed frequency clock signal and a digital equalization word are input to generate phase information corresponding to the current phase of a sine wave at every clock period, and generate an amplitude information signal according to the output phase information of the phase accumulator. .

상기 메모리의 디지탈 출력을 샘플링신호에 따라 아나로그신호로 변환하고, 상기 D/A변환기의 출력을 저역통과필터링하여 정형화된 신호를 발생한다.The digital output of the memory is converted into an analog signal according to a sampling signal, and the output of the D / A converter is low-pass filtered to generate a shaped signal.

Description

Direct Digital Synthesis Method and Circuit Using Phase Accumulator

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 회로도.2 is a circuit diagram according to the present invention.

Claims

A digital synthesizer, comprising: a phase accumulator for inputting a fixed frequency clock signal and a digital tuning word to generate phase information corresponding to a current phase of a sine wave at every clock period, and an amplitude information signal according to the output phase information of the phase accumulator A memory for generating a signal, a D / A converter for converting the digital output of the memory into an analog signal according to a sampling signal, and a low pass filter for low-pass filtering the output of the D / A converter to generate a shaped signal. Direct digital synthesis circuit using a phase accumulator, characterized in that the configuration.

2. The direct digital synthesis circuit using a phase accumulator according to claim 1, wherein the memory comprises a ROM having a fixed phase information and a RAM generating an amplitude information signal according to the phase information of the ROM.

In the digital synthesis method, a fixed frequency clock signal and a digital tuning word are input to generate phase information corresponding to the current phase of a sine wave at every clock period, and an amplitude information signal is generated according to the output phase information of the phase accumulator. And converting an analog signal according to the sampling signal and low-pass filtering the output of the D / A converter to generate a shaped signal.

※ Note: The disclosure is based on the initial application.