KR930011159A - Device isolation structure of semiconductor device and manufacturing method thereof - Google Patents

Device isolation structure of semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
KR930011159A
KR930011159A KR1019910019901A KR910019901A KR930011159A KR 930011159 A KR930011159 A KR 930011159A KR 1019910019901 A KR1019910019901 A KR 1019910019901A KR 910019901 A KR910019901 A KR 910019901A KR 930011159 A KR930011159 A KR 930011159A
Authority
KR
South Korea
Prior art keywords
semiconductor device
spacer
nitride film
field region
buffer
Prior art date
Application number
KR1019910019901A
Other languages
Korean (ko)
Inventor
윤찬수
윤주영
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910019901A priority Critical patent/KR930011159A/en
Publication of KR930011159A publication Critical patent/KR930011159A/en

Links

Abstract

본 발명은 반도체장치의 구조 및 그 제조방법에 관한 것으로, 특히 필드영역의 산화공정시 버즈비크와 같은 측면산화 및 불순물의 측면확산등을 최소하할 수 있는 LOCOS 소자분리방법에 있어서, 기판실리콘위에 액티브영역을 보호하기 위한 버퍼층을 패턴 형성하여, 필드영역을 개구하는 공정; 상기 공정후 버퍼층패턴의 버퍼산화막을 안쪽으로 소정량 언더컷에칭시키는 공정; 이어서, 상기 결화물 전면에 질화박막을 침적하는 공정, 이어서, 채적팽창이 가능한 물질로 상기 질화박막 측벽에 스페이서를 형성하고 이 스페이서를 마스크로 하여 질화박막을 에칭하는 공정; 이어서 개구된 필드영역을 산화시키는 공정으로 이루어진 것을 특징으로 하는 본 발명에 의하면 버퍼층패턴 하부의 버퍼산화막 측면을 소정량 언더컷 에칭하여 “T ”자의 역형태로 질화박막을 채워 차단하므로써 버퍼산화막의 측면 산화현상인 버즈비크를 거의 완전하게 제거할 수 있으며, 필츠영역의 산화공정시 스페이서의 체적팽창을 이용하여 질화박막의 리프팅을 최소화하면서 필드영역의 평탄도를 양호하게 할 수 있을 뿐 아니라, 스페이서폭 만큼 채널지지 이온의 측면확산 여유를 가지므로 필드 영역이내로 채널저지 이온충을 한정시키게 되어 반도체자치의 고집적화 및 전기적 특성을 크게 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device and a method of manufacturing the same. In particular, in a LOCOS device isolation method capable of minimizing side oxidation such as Buzzbee and side diffusion of impurities during an oxidation process of a field region, Patterning a buffer layer for protecting the active region and opening the field region; Performing a step of undercut etching the buffer oxide film of the buffer layer pattern inward after the step; Subsequently, a step of depositing a thin nitride film on the entire surface of the nitride, and then forming a spacer on the side wall of the thin nitride film with a material capable of stack expansion, and etching the nitride film using the spacer as a mask; Next, according to the present invention, a step of oxidizing the open field region is performed by undercut etching a predetermined amount of the underside of the buffer oxide layer under the buffer layer pattern to fill and block the thin nitride film in an inverted form of “T” to laterally oxidize the buffer oxide layer. The phenomenon of Buzzbeek can be almost completely removed, and the flatness of the field region can be improved as well as the spacer width by minimizing the lifting of the thin film by using the volume expansion of the spacer during the oxidation process of the Pilz region. Since the channel diffusion ions have a side diffusion margin, the channel blocking ion charges are limited within the field region, thereby greatly increasing the integration and electrical characteristics of the semiconductor autonomy.

Description

반도체장치의 소자분리구조 및 그 제조방법Device isolation structure of semiconductor device and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3A도에서 제3E도는 본 발명의 방법에 의한 LOCOS 소자분리의 형성공정 순서단면도이다.3A through 3E are sectional views of a process for forming LOCOS device isolation by the method of the present invention.

Claims (10)

반도체장치의 LOCOS 소자분리영역에 있어서, 실리콘 기판위의 액티브 영역에 버퍼층이 적층되어서 질화막밑의 패드산화막이 액티브영역 안쪽으로 소정량 언더컷 에칭되어 있는 버퍼층패턴과, 상기 버퍼층패턴 축벽에 “T ”자의 역상으로 질화박막이 위치하고, “T ”자의 역상 한쪽 면에는 스페이서가 구비되어 필드영역이 개구된 것을 특징으로 하는 반도체장치의 구조.In the LOCOS device isolation region of a semiconductor device, a buffer layer is stacked in an active region on a silicon substrate so that a pad oxide film under a nitride film is undercut etching a predetermined amount into the active region, and a “T” character is formed on the axis of the buffer layer pattern axis. A structure of a semiconductor device, characterized in that a thin nitride film is placed in a reverse phase, and a spacer is provided on one side of the reverse phase of the letter “T” to open a field region. 제1항에 있어서, 상기 스페이서는 필드영역의 선택산화공정시 채적팽창이 가능한 물질인 것을 특징으로 하는 반도체장치의 구조.The structure of a semiconductor device according to claim 1, wherein the spacer is a material capable of stack expansion during the selective oxidation of the field region. 제2항에 있어서, 상기 체적팽창이 가능한 물질로는 폴리실리콘, 또는 고온열산화막의 어느 하나인 것을 특징으로 하는 반도체장치의 구조.3. The structure of a semiconductor device according to claim 2, wherein the material capable of volume expansion is any one of polysilicon or a high temperature thermal oxide film. 제1항 및 제2항에 있어서, 상기 스페이서는 채널저지이온을 실리콘 계면에 주입시킬 때의 이온주입마스크인것을 특징으로하는 반도체 장치의 구조.The structure of a semiconductor device according to claim 1 or 2, wherein said spacer is an ion implantation mask when implanting channel blocking ions into a silicon interface. 반도체장치의 LOCOS 소자분리 방법에 있어서, 기판실리콘 위에 액티브영역을 보호하기 위한 버퍼층을 패턴 형성하여, 필드영역을 개구하는 공정; 상기 공정후 버퍼층 패턴의 버퍼산화막을 안쪽으로 소정량 언더컷에칭시키는 공정; 이어서, 상기 결과물 전면에 질화박막을 침적하는 공징, 이어서 체적팽창이 가능한 물질로 상기 질화박막 측벽에 스페이서를 형성하고 이 스페이서를 마스크로 하여 질화박막을 에칭하는 공정; 이어서 개구된 필드영역을 산화시키는 공정으로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.A LOCOS device isolation method of a semiconductor device, comprising: patterning a buffer layer for protecting an active region on a substrate silicon to open a field region; Performing a step of undercut etching the buffer oxide film of the buffer layer pattern inward after the step; A process of depositing a thin nitride film on the entire surface of the resultant, followed by forming a spacer on the sidewall of the thin nitride film with a material capable of volume expansion, and etching the nitride thin film using the spacer as a mask; And subsequently oxidizing the open field region. 제5항에 있어서, 상기 버퍼층 패턴은 버퍼산화막, 버퍼질화막을 순차로 적층 형성하여 사진식각공정에 의해 필드영역을 개구하여서 생긴 패턴인 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 5, wherein the buffer layer pattern is a pattern formed by sequentially stacking a buffer oxide film and a buffer nitride film to open a field region by a photolithography process. 제5항에 있어서, 상기 버퍼층패턴 밑에 있는 버퍼산화막의 언더컷 공정은 불산(HF)에 의한 습식식각공정인것을 특징으로 하는 반도체장치의 제조방법.The method of claim 5, wherein the undercut process of the buffer oxide layer under the buffer layer pattern is a wet etching process using hydrofluoric acid (HF). 제5항 및 제7항에 있어서, 상기 언더컷된 버퍼산화막 부위는 질화박막 침적공정시 질화막에 의해 채워지는것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 5, wherein the undercut buffer oxide film portion is filled by a nitride film during a nitride film deposition process. 제5항에 있어서, 상기 스페이서는 폴리실리콘, 또 고온열산화막의 어느 하나로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 5, wherein the spacer is made of any one of polysilicon and a high temperature thermal oxide film. 제5항 및 제9항에 있어서, 상기 스페이스는 이방성식각인 전면에치백공정에 의해 형성되는 것임을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 5 or 9, wherein the space is formed by an entire surface etching back process in anisotropic etching. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910019901A 1991-11-09 1991-11-09 Device isolation structure of semiconductor device and manufacturing method thereof KR930011159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910019901A KR930011159A (en) 1991-11-09 1991-11-09 Device isolation structure of semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019901A KR930011159A (en) 1991-11-09 1991-11-09 Device isolation structure of semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
KR930011159A true KR930011159A (en) 1993-06-23

Family

ID=67348335

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910019901A KR930011159A (en) 1991-11-09 1991-11-09 Device isolation structure of semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR930011159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020015891A (en) * 2000-08-23 2002-03-02 강정희 A making method for adhesive
KR20180030150A (en) * 2015-07-17 2018-03-21 로저스 저매니 게엠베하 A substrate for an electric circuit and a method for producing a substrate of the above type

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020015891A (en) * 2000-08-23 2002-03-02 강정희 A making method for adhesive
KR20180030150A (en) * 2015-07-17 2018-03-21 로저스 저매니 게엠베하 A substrate for an electric circuit and a method for producing a substrate of the above type

Similar Documents

Publication Publication Date Title
US5369052A (en) Method of forming dual field oxide isolation
JPH04346229A (en) Method of separating element of semiconductor device
JP2802600B2 (en) Method for manufacturing semiconductor device
JPH06216120A (en) Method of forming electrical isolation structure of integrated circuit
KR930011159A (en) Device isolation structure of semiconductor device and manufacturing method thereof
KR940012575A (en) Trench isolation manufacturing method of semiconductor device
CN100414681C (en) Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolating material
JPH0729971A (en) Manufacture of semiconductor device
JPS63204746A (en) Manufacture of semiconductor device
JPH02117150A (en) Manufacture of semiconductor device
US5541136A (en) Method of forming a field oxide film in a semiconductor device
JPS63288042A (en) Manufacture of semiconductor device
JPH04267336A (en) Manufacture of semiconductor device
KR100257063B1 (en) Method of etching insulation film of semiconductor device
KR0167260B1 (en) Manufacture of semiconductor device
KR940011745B1 (en) Semiconductor device isolation method
KR910009741B1 (en) Manufacturing method of semiconductor device
KR100240277B1 (en) Method of forming an element field oxide film in a semiconductor device
KR930005158A (en) Manufacturing Method of Semiconductor Device
JPS6258656A (en) Manufacture of semiconductor device
KR950021402A (en) Trench type isolation film formation method
KR940012576A (en) Trench isolation manufacturing method
JPS58175843A (en) Manufacture of semiconductor integrated circuit
KR950009966A (en) Device Separation Method of Semiconductor Device
JPS63278328A (en) Manufacture of semiconductor capacitor

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
WITB Written withdrawal of application