KR930011056B1 - Methoid of manufacturing cap poliside bit line - Google Patents
Methoid of manufacturing cap poliside bit line Download PDFInfo
- Publication number
- KR930011056B1 KR930011056B1 KR1019900022048A KR900022048A KR930011056B1 KR 930011056 B1 KR930011056 B1 KR 930011056B1 KR 1019900022048 A KR1019900022048 A KR 1019900022048A KR 900022048 A KR900022048 A KR 900022048A KR 930011056 B1 KR930011056 B1 KR 930011056B1
- Authority
- KR
- South Korea
- Prior art keywords
- bit line
- forming
- polysilicon
- silicide
- tisi
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 4
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 13
- 239000002019 doping agent Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910008486 TiSix Inorganic materials 0.000 abstract 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 abstract 1
- 235000011114 ammonium hydroxide Nutrition 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000003504 photosensitizing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1도는 종래의 공정단면도.1 is a conventional cross-sectional view of the process.
제2도는 본 발명의 공정단면도.2 is a cross-sectional view of the process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : LTO1: substrate 2: LTO
3 : 폴리실리콘 4 : Ti3: polysilicon 4: Ti
5 : TiSiX6 : TiSi2 5: TiSi X 6: TiSi 2
7 : IMD7: IMD
본 발명은 캡 폴리사이드 비트라인 제조방법에 관한 것으로 특히 배선공정에 있어서 배선의 저항을 낮추어 공정의 안정성을 높이기에 적당하도록 한 것이다.The present invention relates to a method for manufacturing a cap polyside bit line, and in particular, to reduce the resistance of the wiring in the wiring process so as to increase the stability of the process.
종래의 배선공정을 제1(a)도에 도시된 바와같이 기판(11)위에 게이트 산화막(12)과 게이트 폴리(13)를 형성하고 패터닝한후 측벽(14)을 형성한다. 그리고 기판(11)과 비트라인을 격리시키기 위해 LTO(15)를 형성하고 접촉상(contact window)을 형성한후 전도성을 부여하기 위해 도펀트를 도핑한다.In the conventional wiring process, as shown in FIG. 1A, the gate oxide film 12 and the gate poly 13 are formed and patterned on the substrate 11, and then the sidewalls 14 are formed. The LTO 15 is formed to isolate the substrate 11 from the bit line, a contact window is formed, and then the dopant is doped to impart conductivity.
다음에 (b)와같이 폴리실리콘(16)과 실리사이드(17)를 형성하고 (c)와 같이 포트/에치공정을 통해 상기 폴리실리콘(16)과 실리사이드(17)를 패터닝하여 비트라인을 형성한다.Next, polysilicon 16 and silicide 17 are formed as shown in (b), and the polysilicon 16 and silicide 17 are patterned through a port / etch process as in (c) to form a bit line. .
그리고 폴리의 도펀트를 활성화시키고 실리사이드(17)의 저항을 낮추기 위하여 어닐링(Annealing)공정을 실시한다. 또한, 비트라인과 그 위의 전도성 물질을 격리시키기 위해 IMD(18)를 형성한다. 그러나, 상기와 같은 종래 방법에 있어서는 비트라인 형성후 비트라인의 측벽으로 산소침입이 발생하여 폴리실리콘(16)과 실리사이드(17)사이에 필링(Peeling)이 일어나기 쉽다.In order to activate the dopant of the poly and lower the resistance of the silicide 17, an annealing process is performed. In addition, an IMD 18 is formed to isolate the bit line and the conductive material thereon. However, in the conventional method as described above, after the bit line is formed, oxygen intrusion occurs into the sidewall of the bit line, and peeling occurs easily between the polysilicon 16 and the silicide 17.
그리고 비트라인 에치시 폴리실리콘(16)과 실리사이드(17)의 계면에서의 빠른 식가율 때문에 노칭(Notching)이 일어나며, 비트라인 포토공정 진행시 실리사이드(17)의 높은 반사율과 웨이퍼의 심한 단차로 인해 감광제의 노칭현상이 발생하였다. 본 발명은 이와같은 종래의 결점을 해결하기 위하여 안출한 것으로 이하에서 본 발명의 실시예를 첨부된 도면 제2도에 의하여 상세히 설명하면 다음과 같다.In addition, notching occurs due to the fast etch rate at the interface between the polysilicon 16 and the silicide 17 during bit line etching, and due to the high reflectivity of the silicide 17 and the severe step of the wafer during the bit line photo process. Notching phenomenon of the photosensitizer occurred. The present invention has been made to solve the above-mentioned drawbacks as described in detail below with reference to the accompanying drawings, embodiments of the present invention 2 as follows.
먼저 (a)와 같이 기판(1)위에 통상의 공정에 의해 트랜지스터를 형성하고 기판(1)과 비트라인을 격리시키기 위하여 LTO(2)를 형성한후 포토/에칭공정을 통하여 비트라인과 기판(1)이 접촉하도록 접촉창을 형성한다. 그리고 폴리실리콘(3)을 형성하고 전도성을 부여하기 위해 도펀트를 도핑하며 (b)와 같이 포토/에치 공정을 통해 비트라인을 형성한다. 이어서 (c)와 같이 전표면위에 Ti(4)를 형성하고 실리사이드 형성을 위해 600~700CN2분위기에서 30~60초간 제1리액션(Reaction)을 실시하며 이때 폴리실리콘(3) 주위의 Ti(빗금친 부분은 폴리실리콘과 Ti의 계면을 나타냄)는 실리콘과 반응하여 초기형태의 TiSiX를 형성하고 LTO(2)위의 Ti(4)는 반응을 일으키지 않아 그대로 존재한다.First, as shown in (a), a transistor is formed on the substrate 1 by a conventional process, and an LTO 2 is formed to isolate the substrate 1 from the bit line, and then, through the photo / etching process, the bit line and the substrate ( 1) form a contact window to make contact. Then, the polysilicon 3 is formed and doped with a dopant to impart conductivity, and a bit line is formed through a photo / etch process as shown in (b). Subsequently, Ti (4) is formed on the entire surface as shown in (c), and 600 to 700 for silicide formation. In the CN 2 atmosphere, the first reaction is performed for 30 to 60 seconds. At this time, Ti around the polysilicon 3 (hatched portion represents the interface between polysilicon and Ti) reacts with silicon to form TiSi X. And Ti (4) on the LTO (2) does not react and is present as it is.
다음에 (d)와 같이 LTO(2)위의 미반응된 Ti(4) 및 TiN을 제거하고 폴리실리콘(3) 주위에 형성된 TiSiX(5)를 남겨놓기 위하여 NH4OH : H2O2=1 : 1조건의 용액에 3~7분간 담근다.Next, in order to remove unreacted Ti (4) and TiN on LTO (2) and leave TiSi X (5) formed around the polysilicon (3) as shown in (d), NH 4 OH: H 2 O 2 = 1: Soak for 3-7 minutes in 1 condition solution.
그리고 TiSiX(5)의 제2리액션을 800℃이상에서 30~60초간 실시하면 TiSiX가 TiSi2(2)로 변환되고 마지막 공정으로 (e)와 같이 비트라인과 그위의 전도물질을 격리시키기 위하여 IMD(7)를 형성한다.If the second reaction of TiSi X (5) is carried out for 30 to 60 seconds at 800 ° C. or higher, TiSi X is converted into TiSi 2 (2), and finally, as in (e), the bit line and the conductive material thereon are isolated. To form an IMD 7.
이상에서 설명한 바와같은 본발명에 의하면 폴리실리콘(3)과 TiSi2(6)의 실리사이드 사이의 계면이 외부에 노출되지 않으므로 필링현상을 방지할 수 있으며, 폴리실리콘(3)만을 에치하므로 비트라인 에치시 실리사이드/폴리실리콘(3)계면의 노칭현상과 비트라인 포토공정에서 실리사이드의 높은 반사율로 인하여 발생하는 감광제의 노칭현상을 방지할 수 있을 뿐만 아니라 TiSi2(6)가 차지하는 면적이 기존에 비해 넓어져 같은 두께의 비트 라인에서 보다 더 낮은 저항을 얻을 수 있는 효과가 있다.According to the present invention as described above, since the interface between the silicide of the polysilicon (3) and the TiSi 2 (6) is not exposed to the outside, peeling can be prevented, and only the polysilicon (3) is etched into the bit line. Not only does notching of the photosilicide / polysilicon (3) interface and the photoresist due to the high reflectivity of silicide in the bit line photo process, but also the area occupied by TiSi 2 (6) is larger than before. The result is that a lower resistance can be obtained than with a bit line of the same thickness.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900022048A KR930011056B1 (en) | 1990-12-27 | 1990-12-27 | Methoid of manufacturing cap poliside bit line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900022048A KR930011056B1 (en) | 1990-12-27 | 1990-12-27 | Methoid of manufacturing cap poliside bit line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920013674A KR920013674A (en) | 1992-07-29 |
| KR930011056B1 true KR930011056B1 (en) | 1993-11-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900022048A KR930011056B1 (en) | 1990-12-27 | 1990-12-27 | Methoid of manufacturing cap poliside bit line |
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| Country | Link |
|---|---|
| KR (1) | KR930011056B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2604107B1 (en) * | 2001-08-09 | 2018-10-10 | Northwest Plant Breeding Company | Wheat plants having increased resistance to imidazolinone herbicides |
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1990
- 1990-12-27 KR KR1019900022048A patent/KR930011056B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR920013674A (en) | 1992-07-29 |
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