KR930010930B1 - Moving picture compensating circuit - Google Patents

Abstract

The circuit consists of an edge detecting part for detecting the edge of brightness signals separated from the complex video signal converted to digital, a moving picture interpolating part for delaying the brightness signals by a fixed time when the brightness is for a moving picture and for generating interpolating information through the pixels desiring interpolation by evaluating the delayed time. A control switch is incorporated in the circuit for detecting the output of the moving picture interpolating part.

Description

Donghwa Interpolation Circuit

1 is a block diagram of a composite video signal material tod system including a moving picture interpolation circuit according to the present invention.

FIG. 2 is an embodiment of the edge detector of FIG. 1, where (a) is a detailed circuit diagram and (b) shows an arrangement of pixels.

FIG. 3 is an embodiment of the moving picture interpolation unit of FIG. 1, wherein (a) is a detailed circuit diagram and (b) shows an arrangement of pixels.

* Explanation of symbols for the main parts of the drawings

1: luminance / chromatic signal separation unit 2: first A / D converter

3: still picture interpolation unit 4: moving picture interpolation unit

5: edge detector 6: first D / A converter

7: second A / D converter 8: chromaticity signal processor

9: 2D / A converter AD1-8: 1st-8th adder

D1 to 19: 1 to 19 delay means SW1: control switch

25 threshold setting means

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture interpolation circuit in a recording and reproducing system for digital signal processing of a video signal, and more particularly to a moving picture interpolation circuit for improving resolution during moving picture reproduction.

As a system for recording and reproducing an image (or video) signal, a video cassette recorder (hereinafter, abbreviated as VCR) is one example. In such a recording and reproducing system, the technology for high resolution and high image quality is a subject of continuous research. As a result, the generation of a signal is changed from an analog processing method to a digital processing method, and a technology for accurately detecting a high frequency signal by compressing a signal processing band has also emerged. A practical example of a technique for processing a full-band video signal on a compressed bandwidth is a luminance signal as disclosed in Korean Patent Application No. 07-569029, filed with Samsung Electronics Co., in the United States. Superimposing the high frequency component of the luminance signal on the low frequency component of the luminance signal to record and reproduce the video (or TV) signal of the full bandwidth on a recording medium of limited bandwidth. However, the technique described in No. 07-569029 described above records high frequency components superimposed on low frequency components regardless of moving pictures or still pictures, and during playback, detects moving pictures by spatial filtering and detects still pictures by temporal filtering. Done. In particular, in the case of moving pictures, since the linecomb filter is used to detect and compare the amplitude between pixels of the same image having a phase difference of 180 °, the vertical resolution of the image is reduced.

Accordingly, it is an object of the present invention to provide a moving picture interpolation circuit for interpolating a blank area between pixels having a predetermined phase difference in order to increase the resolution of moving pictures in a recording and reproducing system for digital signal processing of a production signal.

In order to achieve the above object, the present invention provides a video interpolation circuit of a system for recording and reproducing a composite video signal by a de-zillar signal processing method; An edge detector for detecting an edge of the luminance signal separately output from the composite video signal digitally signaled by the digital signal processing method; A moving picture interpolation unit for delaying the current brightness signal and the 1H delayed brightness signal by a predetermined value and outputting interpolation information by peripheral pixels in a region to be interpolated by calculating a delayed value when the brightness signal is a moving picture; And a control switch for selecting and outputting an output signal of the moving image interpolation unit when the luminance signal is a moving image by the output signal of the edge detection unit.

Next, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a composite video signal system including a moving picture interpolation circuit according to the present invention. Here, the composite video signal reproducing system is capable of reproducing an improved video signal than the conventional VHS system.

The configuration of FIG. 1 includes the luminance / chromatic signal separator 1 connecting the composite video signal picked up from the recording medium to the input terminal and the input terminal connected to the output terminal of the luminance / chromatic signal separating unit 1, respectively. Still image interpolation unit 3, moving picture interpolation unit 4, and edge detection unit, each of which has an input terminal connected to the / D converter 2 and the second A / D converter 7, and the output terminal of the first A / D converter 2, respectively. (5) and the output terminal of the still picture interpolation section 3 to the first contact point S1, and the output terminal of the moving picture interpolation section 4 to the second contact point S2 to the output signal of the edge detection section 5; The input terminal is connected to the output terminal of the control switch SW1 controlled by the control switch SW1, the first D / A converter 6 connected to the reference contact S0 of the control switch SW1, and the second A / D converter 7; The connected chroma signal processor 8, the second D / A converter 9 connected to the output terminal of the chroma signal processor 8, the first D / A converter 6 and the second D / A converter 9 Connect the input terminal to the output terminal of the When composed of a first adder (AD1) for outputting a composite video signal to be displayed on the means (not illustrated in the figure).

FIG. 2 is an embodiment of the edge detector 5 of FIG. 1 to accurately detect a high frequency signal region. FIG. 2A is a detailed circuit diagram, and FIG. 2B is a fragmentary diagram showing the arrangement of pixels on the image display means (not illustrated).

2A includes a first delay circuit D1 (10) for separately outputting the luminance signal from the luminance / chromatic signal separation unit 1 and passing through the first A / D converter 2 to an input terminal, The first delay means 21 and the second delay means 22, each of which is connected to the output end of the delay circuit 10, and the output ends of the first delay means 21 and the second delay means 22, respectively. A first logic operation unit 23 connecting the input terminal, a second logic operation unit 24 connecting the input terminal to the output terminal of the first logic operation unit 23, threshold presetting means 25 for moving pictures, and a second A comparison circuit 20 is formed by connecting each input terminal to the output terminal of the logic operation unit 24 and the threshold presetting means 25 and the output terminal to the control switch SW1.

More specifically, the first delay means 21 has a second delay circuit (D2) (11) connecting the input terminal to the output terminal of the first delay circuit 10, and the input terminal to the output terminal of the second delay circuit (11). And a third delay circuit (D3) 12 connected, and a fourth delay circuit (D4) 13 in which an input is connected to an output terminal of the third delay circuit (12). The second delay means 22 includes a fifth delay circuit (D5) 14 having an input terminal connected to an output terminal of the first delay circuit 10, and a sixth input terminal connected to an output terminal of the fifth delay circuit 14. An input terminal is connected to an output terminal of the seventh delay circuit (D7) 16 and an output terminal of the delay circuit (D6) 15, an output terminal of the sixth delay circuit (15). An eighth delay circuit (D8) 17.

The first logical operation means 23 connects one input terminal to the output terminal of the fourth delay circuit 13 of the first delay means 21 and the output terminal of the seventh delay circuit 16 of the second delay means 22. The input terminal is connected to the output terminal of the second adder AD2 connecting the other input terminal, the third delay circuit 12 of the first delay means 21 and the eighth delay circuit 17 of the second delay means 22. Connect the connected output terminals of the first inverter IN1 and the first inverter IN1 and the third adder AD3 connected to the input terminals of the connected third adder AD3 and the output terminal of the second adder AD2. It consists of one 4th adder AD4. The second logical operation means 24 comprises a ninth delay circuit D9 (18) connected with an input terminal to the control signal output terminal of the fourth adder AD4 in the first logical operation means 23, and the fourth adder AD4. A tenth delay circuit (D10) (19) having an input connected to the information output terminal of < RTI ID = 0.0 >), < / RTI > Is done.

FIG. 3 is an embodiment of the moving picture interpolation unit 4 of FIG. 1, in which a plurality of delays are applied to a circuit that has been spatially processed using a line comb filter to process moving pictures in a conventional improved video signal reproduction system. A circuit and logic operation means are added to output the interpolated luminance signal. FIG. 3A is a detailed circuit diagram, and FIG. 3B is a fragmentary diagram showing the arrangement of pixels on the image display means (not illustrated).

The configuration shown in FIG. 3A includes third delay means 35 which connects the current line luminance signal outputted through the output terminal of the first A / D converter 2 to the input terminal, and a luminance signal obtained by delaying the current line luminance signal by 1H period. Is connected to an output terminal of the fourth delay means 36, the third delay means 35 and the fourth delay means 36 connected to the input terminal, and is output to the second contact point S2 of the control switch SW1. It consists of the third logical operation means 37 which is connected.

More specifically, the third delay means 35 includes an eleventh delay circuit D11 24 for connecting the current line luminance signal to the input terminal and a twelfth delay circuit for connecting the input terminal to the output terminal of the eleventh delay circuit 24. (D12) 25, the thirteenth delay circuit (D13) 26 having an input terminal connected to the output terminal of the twelfth delay circuit 25, and the fourteenth delay terminal connected to the output terminal of the thirteenth delay circuit 26; A delay circuit D14 (27). The fourth delay means 36 includes a fifteen delay circuit (D15) 29 for connecting the 1H delayed luminance signal to the input terminal, and a sixteenth delay circuit (D16) for connecting the input terminal to the output terminal of the fifteen delay circuit (29). (30), the 17th delay circuit (D17) 31 which connects the input terminal to the output terminal of the 16th delay circuit 30, and the 18th delay circuit which connected the input terminal to the output terminal of the 17th delay circuit 31 ( D18) 32 and a nineteenth delay circuit (D19) 33 in which an input terminal is connected to an output terminal of the eighteenth delay circuit 32. The third logical operation means 37 includes a fifth adder AD5 connecting the respective input ends to the output end of the twelfth delay circuit 14th delay circuit 27 of the third delay means 35, and the fifth adder AD5. A sixth attenuator 28 having an input terminal connected to an output terminal of the < RTI ID = 0.0 >) < / RTI > and an input terminal connected to the output terminals of the fifteen delay circuit 29 and the nineteenth delay circuit 33 of the fourth delay means 36, respectively. A second attenuator 34 having an input end connected to the adder AD6, an output end of the sixth adder AD6, a second inverter IN2 having an input end connected to the output end of the second attenuator 34, and a second one. The output terminal of the seventh adder AD7 connected to the output terminal of the inverter IN2 and the first attenuator 28, and the seventeenth adder AD7 and the seventeenth delay circuit 31 of the fourth delay means 36. And an eighth adder AD8 having an input terminal connected to each of them and an output terminal connected to the second contact point S2 of the control switch SW1.

The operation of FIG. 1 will then be described in conjunction with FIGS. 2 and 3.

First, since the circuit shown in FIG. 1 is an example applied to an improved video signal reproducing system, the remaining block diagrams except for the moving picture interpolation unit 4 and the edge detection unit 5 are the same as before. That is, the luminance / chromatic signal separator 1 outputs the composite video signal picked up from the recording medium into luminance and chroma signals, and the first A / D converter 2 outputs the luminance / chromatic signal separator 1 from the luminance / chromatic signal separator 1. The luminance signal is converted into digital information, and the second A / D converter 7 converts the chroma signal output from the luminance / chromatic signal separation unit 1 into digital information. The still picture interpolation unit 3 processes the signal output from the first A / D converter 2 in time using a frame comb filter or the like. The moving picture interpolation unit 4 adds a circuit as shown in FIG. 3A to a circuit that has been spatially processed using a conventional line comb filter or the like, and outputs interpolated information on a portion where no pixel between pixels is loaded. Details thereof will be described with reference to FIG. 3A. The edge detection unit 5 detects whether a moving picture or a still picture is detected by detecting the relationship between the pixels placed in the diagonal direction by using a plurality of delay circuits and logic operation means. Details will be given in the description of the operation of FIG.

The control switch SW1 selects and passes one of the output of the still image interpolation unit 3 and the output of the moving image interpolation unit 4 according to the output signal of the edge detection unit 5. The first D / A converter 6 converts the signal output from the control switch SW1 into an analog signal.

On the other hand, the chromaticity digital signal output from the second A / D converter 7 processes the chromaticity signal for the same time as the time taken until the luminance signal is output from the chromaticity signal processor 8 to the first D / A converter 6. . The second D / A converter 9 converts the chroma signal output from the chroma signal processor 8 into an analog signal.

The first adder AD1 adds the luminance and chroma signals output from the first D / A converter 6 and the second D / A converter 9 and outputs them in the form of a composite video signal before recording.

The luminance / chromatic signal separation unit 1, the first A / D converter 2, the still picture interpolation unit 3, the control switch SW1, the first D / A converter 6, and the second A / D converter 7 ), The chromaticity signal processor 8, the 2D / A converter 9, and the first adder AD1 are used in the improved video signal reproduction system disclosed in the above-mentioned U.S. Patent Application No. 07-569029. Same as

In the operation of FIG. 2, when the luminance signal output from the first A / D converter 2 is applied, the first delay circuit 10 delays the first delay circuit 10 by one pixel (or pixel) area so that the first and second delay means 21 It is output simultaneously to the input terminal of 22. The first delay means 21 is for delaying the pixels of the line in which the pixels of A and B exist among the pixels shown in FIG. 2B, and the pixels of A and B are sequentially delayed by one pixel. That is, the second to fourth delay circuits 11, 12, and 13 are all delay circuits of one pixel unit. When the A and B pixels of FIG. 2B are applied to the first delay means 21, There is no pixel corresponding to the output signal (assuming only A and B exist), and the pixel corresponding to the output signal of the third delay circuit 12 is B, and corresponds to the output signal of the fourth delay circuit 13. The pixels to be A are sequentially delayed output in this manner. The second delay means 22 is also used to delay the pixels of the line on which the C and D pixels of FIG. 2B are placed at the same time as the first delay means 21. All of the fifth to eighth delay circuits 14, 15, 16, and 17 are delayed circuits of one pixel unit, and are delayed by the first delay means 21 in the same manner as the delay method. There is no pixel corresponding to the output signal of the circuit 15, the pixel corresponding to the output signal of the seventh delay circuit 16 is D, the pixel corresponding to the output signal of the eighth delay circuit 17 is C.

The first logical operation means 23 adds the information output between the pixels in the diagonal direction with respect to each pixel to the signals output from the first delay means 21 and the second delay means 22 in order to accurately detect the movement state between the pixels. Is to get. That is, the A pixel information which is the output signal of the fourth delay circuit 13 in the first delay means 21 and the output signal of the seventh delay circuit 16 in the second delay means 22 in the second adder AD2. The information of (A + D) is output by adding the D pixel information. Here, the A and D pixel information are pixels in diagonal directions as shown in FIG. 2B.

C pixel information which is the output signal of the third delay circuit 12 in the first delay means 21 and C which is the output signal of the eighth delay circuit 17 in the second delay means 22 in the third adder AD3. The pixel information is added to output information of (B + C). Here, the B and C pixel information are also pixel information in diagonal directions. The (A + D) information output from the second adder AD2 is complemented to 1 through the first inverter IN1 and output as-(A + D). The fourth adder AD4 adds-(A + D), which is the output signal of the first inverter IN1, and (B + C), which is the output signal of the third adder AD3, to add (B + C)-(A Output in the form + D).

The second logical operation means 24 outputs (B + C)-(A + D) information output from the fourth adder AD4 as an absolute value, and the ninth delay circuit 18 supplies a fourth value. When the Sign (or Carry) signal for the (+) and (-) signs of the added value is applied at the control signal output terminal of the adder AD4, the signal is delayed by one pixel area and the tenth delay circuit 19 is outputted. The signal output from the information output terminal of the four adder AD4 is delayed for a period equal to the delay time of the ninth delay circuit 18 and output. In this case, the ninth and tenth delay circuits 18 and 19 may substitute a buffer. The exclusive logic gate XOR is output by being exclusively logic with respect to the signals output from the ninth delay circuit 18 and the tenth delay circuit 19. That is, when the result value added by the fourth adder AD4 becomes positive, the ＂L＂ signal is applied to the ninth delay circuit 18 to the control signal output terminal and the information output from the information output terminal ((B + C)). -(A + D)) is applied to the tenth delay circuit (19).

The ninth and tenth delay circuits 18 and 19 simultaneously apply the applied signal to the input terminal of the exclusive logic gate (XOR). When the exclusive logic gate XOR is a positive sign, the output of the fourth adder AD4 should be output as it is. Therefore, the exclusive logic gate XOR is applied from the ninth delay circuit 18 to the exclusive logic gate XOR. The information is low logic. On the other hand, when the addition result of the fourth adder AD4 becomes negative, the signal output from the ninth delay circuit 18 becomes high logic, and thus the output of the fourth adder AD4 output through the tenth delay circuit 19. Invert the signal. Therefore, the signal output from the second logical operation means 24 always becomes the value of (B + C)-(A + D) |. Here, the control signal applied from the fourth adder AD4 to the ninth delay circuit 18 is a carry signal, and if the result value is positive, the low logic level signal is output, and if it is negative, the high logic level signal is automatically output.

The threshold value presetting means 25 determines in advance any reference value (threshold value Ki) that can be compared with respect to the resultant value K (proportional gain) according to the motion detection output from the second logical operation means 24. It is stored and output together when there is an output signal from the second logical operation means 24 and compared in the comparison circuit 20. The comparison circuit 20 is a moving picture when the K value output from the second logical operation means 24 is larger than the Ki value, and is determined to be stationary when it is smaller than the Ki value and applied to the control switch SW1. Therefore, if the Ki value is large, the control switch SW1 outputs the output signal of the still image interpolation unit 3 to the first D / A converter 6, and if the Ki value is small, the control switch SW1 is the moving image interpolation unit 4; ) Is outputted to the first D / A converter 6.

FIG. 3 is for detecting pixel interpolation information in an area denoted by α in FIG. 3b (ie, an empty area between pixels having a phase difference of 180 °). The operation of the third delay means 35 The pixels of the line containing the pixels are sequentially delayed output by one pixel. The sequential delay output is the same as the first and second delay means 21 and 22, but the position of the pixel is a pixel sampled by subsampling and corresponds to one field. The technique for subsampling is a technique known for sampling every other pixel. Therefore, the signal output from the eleventh delay circuit 24 is for the empty pixel region, the signal output from the twelfth delay circuit 25 is for the D pixel, and the signal output from the thirteenth delay circuit 26 is For the empty pixel area, the signal output from the fourteenth delay circuit 27 is for the E pixel. The fourth delay means 36 sequentially delay the first, second, and third delay means 21, 22, and 35 with respect to the line on which the A, B, and C pixels of FIG. 3B are placed. Therefore, the signal output from the fifteenth delay circuit 29 is for the C pixel, the signal output from the sixteenth delay circuit 30 is for the empty pixel area, and the signal output from the seventeenth delay circuit 31 is The signal output from the eighteenth delay circuit 32 is for the B pixel, and the signal output from the nineteenth delay circuit 33 is for the A pixel.

The third logical operation means 37 uses a method of using the image information in the vicinity thereof to obtain interpolation information of the? Region. That is, the interpolation information is outputted by giving the weight of the information in the vertical direction adjacent to the α region with the largest weight and assigning the weight to the left and right components of the information and the vertical information at a constant value. Therefore, the fifth adder AD5 adds D output from the twelfth delay circuit 25 of the third delay means 35 and E output from the fourteenth delay circuit 27 to output (D + E). The sixth adder AD6 adds C output from the fifteenth delay circuit 29 and A signal output from the nineteenth delay circuit 33 to output (A + C). The signals output from the fifth adder AD5 and the sixth adder AD6 are applied to the first and second attenuators 28 and 34, respectively, by weights assigned to predetermined values. Since the attenuation ratios of the first and second attenuators 28 and 34 are set to 1/2, the signals output to the first and second attenuators 28 and 34 are respectively Wow to be. The signal output from the second attenuator 34 is complemented by 1 at the second inverter IN2-( In the form of). The seventh adder AD7 adds a signal output from an output terminal of the first attenuator 28 and the second inverter IN2. Print the value. The eighth adder AD8 adds the B-pixel information of the seventeen adder AD7 and the seventeenth delay circuit 31 of the fourth delay means 36. Is output to the second contact S2 of the control switch SW1. Here, the output value of the eighth adder AD8 becomes interpolation information of the α region.

As described above, the present invention detects a moving state between pixels using diagonal pixels detected by delay circuits and logic operation circuits in a system for processing a digital signal, and gives region information desired for interpolation with different weights. By detecting by the peripheral pixel information, there is an advantage of improving the resolution than before in moving picture reproduction.

Claims (10)

A system for recording and reproducing a composite production signal by a digital signal processing method; An edge detector 5 for detecting an edge of the luminance signal separately output from the composite video signal digitally signaled by the digital signal processing method, and a current luminance signal and 1H delayed luminance when the luminance signal is moving A moving picture interpolation unit 4 for delaying a signal by a predetermined value and outputting interpolation information by peripheral pixels of a region to be interpolated by calculating the delayed value; And a control switch SW1 for selecting and outputting an output signal of the moving image interpolation unit 4 when the luminance signal is a moving image by the output signal of the edge detection unit 5. . 2. The edge detecting unit (5) according to claim 1, wherein the edge detector (5) comprises first delay means (21) having a plurality of delay circuits for delaying pixels of one line of the luminance signal, and pixels of one line following the one line. The first delay means 22 having a plurality of delay circuits for delaying and the output signal of the first delay means 21 and the second delay means 22 are present in the first line and the other one line. First logical operation means 23 for outputting edge information by operating the pixel diagonally, second logical operation means 24 for outputting the result of the first logical operation means, and the luminance signal The control switch by comparing a threshold presetting means 25 for outputting a threshold value already set for the edge signal of the output signal of the second logical operation means 24 and the threshold presetting means 25. A moving picture comprising a comparison circuit 20 for outputting to (SW1) Interpolation circuit. 2. The moving picture interpolation section (4) according to claim 1, characterized in that the moving picture interpolation section (4) includes a third delay circuit (35) having a plurality of delay circuits for delaying one line of the current luminance signal, and one line of the 1H delayed luminance signal. A fourth delay circuit 26 having a plurality of delay circuits for delaying the signal, the third delay circuit 35 and the fourth delay circuit 36 so as to output the interpolation information to the control switch SW1. And a third logical operation means (37) for logical operation of the output of the " 4. The moving picture interpolation circuit according to claim 2 or 3, wherein the delay circuits in the first, second, third, and fourth delay means comprise delay circuits of one pixel unit. 5. The third logical operation means (37) according to claim 4, wherein the third logical operation means (37) has the largest weight for the pixels in the adjacent vertical direction with respect to the interpolation information, and is assigned to the interpolation information and the left and right pixels of the pixel at a constant value. A moving picture interpolation circuit, characterized in that it is calculated to give a weight. The method of claim 4, wherein the first logical operation 23 is output through a signal output from the final output terminal of the first delay means 21 and the delay circuit of the third pixel unit of the second delay means 22. A signal output through a second addition circuit AD2 for adding a signal to be added, a delay circuit in units of secondary pixels of the first delay means 21, and a final output terminal of the second delay means 22. A third addition circuit AD3 for adding a signal, a first inverter IN1 for complementing the output of the second addition circuit AD2 by one, an output of the first inverter IN1, and the third And a fourth addition circuit (AD4) for adding the output of the addition circuit (AD3). The information output terminal of the fourth adding circuit (AD4) according to claim 6, wherein the second logic calculating means (24) is a low logic (signal code) output from the code output terminal of the fourth adding circuit (AD4). And outputting the signal output as it is, and outputting the output signal of the information output terminal if the output signal of the code output terminal is a high logic (sign). The third logical operation means 37 is output through a signal output from the final output terminal of the third delay means 35 and a delay circuit of the second pixel unit of the third delay means 35. A fifth adder AD5 for adding a signal to be added, a signal output from the final output terminal of the fourth delay means 36, and an output signal of a delay circuit of the first pixel unit of the fourth delay means 36; Attenuates the output signal of the sixth adder AD6, the output signal of the fifth adder AD5 by a predetermined value, and attenuates the output signal of the sixth adder AD6 by the predetermined value. Adds the second attenuator 34, the second inverter IN2 for complementing the output of the second attenuator 34, and the outputs of the first attenuator 28 and the second inverter IN2. The control switch by adding the seventh adder AD7, the seventh adder AD7, and the output signal to the delay arc of the third pixel unit of the fourth delay means 36; Moving image interpolation circuit characterized by made of an eighth adder (AD8) for outputting a (SW1). 9. The moving picture interpolation circuit according to claim 8, wherein said delay circuit uses a latch that is a one-clock delay element. 9. The moving picture interpolation circuit according to claim 8, wherein said delay circuit is used as a D flip-flop.