KR930009582B1 - Self-aligned stacked capacitor and manufacturing method thereof - Google Patents

Abstract

The self-aligned stacked capacitor structure and its fabricating process are disclosed. Transistor is formed on the substrate and an oxide layer used for buried contact etch, an undoped polysilicon layer and an oxide layer used for increasing of capacitance are formed on the substrate successively. And a mask is formed on the oxide layer used for increasing of capacitance and then the oxide layer used for increasing of capacitance is etched vertically and the undoped polysilicon layer is etched isotropically to form a protrusive structure, then the mask is removed and the oxide used for buried contact etch is etched selectively to form a buried contact on the impurity region of the transistor. Polysilicon is deposited on the entire surface of the protrusive structure and then a photoresist is coated and etched to expose the oxide used for increasing of capacitance. Then the photoresist is removed and the oxide used for increasing of capacitance is etched by wet etch, and a capacitor dielectric layer and a plate electrode are formed, thereby a cave shaped capacitor having a large capacitance is obtained.

Description

Self-matching Multilayer Capacitor Structure and Manufacturing Method

1 is a conventional process cross-sectional view.

2 is a cross-sectional view of the process of the present invention.

* Explanation of symbols for main parts of the drawings

1 substrate 2 field oxide film

3,5,6,7,9 oxide film 4,8,12 polycrystalline silicon film

3a: gate oxide film 4a: polysilicon gate

5a: gate cap oxide film 11: dielectric film

PR ₁ -PR ₄ : Photosensitizer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor structure and a manufacturing method of a highly integrated Mos Memory device, and more particularly, to a structure and a manufacturing method of a self-matching stacked capacitor.

The conventional multilayer capacitor manufacturing process will now be described in detail with reference to FIGS. 1A to 1R.

First, in order to form a field region and an active region of the field oxide film 21 on the substrate 20 using a conventional LOCOS (Local Oxidation of Silicon) process as shown in FIG. 1A, and then to form a gate of a transistor. The oxide film 22 is grown in a high thermal diffusion furnace, and a polycrystalline silicon film (or a polyside film composed of a polycrystalline silicon film and a silicide film) 23 doped thereon as shown in FIG. 1b and an oxide film 24 for a gate cap. ).

Subsequently, the photoresist PR ₇ is deposited, exposed, and developed to define a word line region, and the oxide layer 24, the polysilicon layer 23, and the oxide layer 22 are etched using the mask as the first c and d diagrams. Thus, word lines are formed on the field oxide layer 21, which is the field region, so that transistors are formed on the active region, respectively.

At this time, the etching process is performed by etching the polycrystalline silicon film 23 and the oxide film 22 vertically by dry etching to form the polycrystalline silicon gate 23a, the gate oxide film 22a, and the gate cap oxide film 24a. After the word line is formed, the source and drain regions are formed by the low concentration ion implantation using the word line as a mask. Then, the photoresist PR ₇ for the transistor forming mask is removed as shown in FIG. 1e. Then, the oxide film 25 is entirely deposited as shown in FIG. 1f. The sidewall oxide layer 25a for preventing the short channel is formed through the etch back process by the reactive ion etching (RIE) method as shown in FIG.

Then, high concentration ion implantation is performed using the sidewall oxide layer 25a as a mask to form a source and drain junction of a lightly doped drain (LDD) structure.

Next, as shown in FIG. 1h, an oxide layer 26 is insulated from the transistor polysilicon gate 23a and the polysilicon layer for the storage node of the capacitor. Then, the contact region is defined using a photoresist PR ₈ , and the contact region is defined. A buried contact is formed so that the junction between the oxide layers 25a and 26 may be connected to the storage node of the capacitor through an etch process using a 1i or the same photoresist PR ₈ as a mask.

Subsequently, the photosensitive agent PR ₇ for forming the buried contact is removed as shown in the 1j chart, and the polysilicon film 27 for the storage node is deposited on the surface of the substrate 20 in the buried contact region as shown in the 1k chart.

After the using the help as a photosensitive agent (PR ₉₎ 1l polycrystalline silicon film 27 over limited and the photosensitive material (PR ₉₎ unnecessary in as claim 1m help to mask the storage node polysilicon film 27 for the storage node The etched portion is removed to form the polycrystalline silicon storage node 27a, and then the photoresist PR ₉ is removed as shown in FIG. 1n.

An oxide Nitride-Oxide (ONO) film 8 is formed as a capacitor dielectric film as shown in FIG. 1O, and a polysilicon film 29 for a plate is deposited thereon.

As a final step, the polysilicon film 29 is defined using the photosensitive agent PR ₁₀ as shown in the 1p diagram, and the polysilicon layer 29 is etched using the photosensitive agent PR ₁₀ as a mask as shown in the 1q diagram. By removing, the polysilicon plate 29a is formed.

The multilayer capacitor is completed by removing the photosensitive agent PR ₁₀ for the polysilicon plate mask as shown in FIG. 1r.

However, the prior art has the following disadvantages.

First, since the capacitance of the capacitor cannot be sufficiently secured, there is a disadvantage in that the refresh characteristics and device reliability of the DRAM are reduced due to the low capacitance.

Second, in order to obtain a capacitor having sufficient capacity, the stack structure must be increased, but it is not suitable for compacting a highly integrated device because the integration of the device is reduced and the area of the chip is increased.

The present invention is to eliminate the above drawbacks to increase the capacitance by increasing the area of the capacitor under the same area of integration to increase the recharging characteristics of the device, as well as to improve the efficiency of the process by using a self-matching process It is an object of the present invention to provide a structure and method of a self-matching capacitor that can improve the characteristics of.

In order to achieve the above object, the present invention, in the step of forming a field region and an active region on a substrate in a conventional manner, and a transistor structure in each of the two regions, the oxide film for etch contact etching and the dough for capacitor expansion as a whole Forming an undoped polycrystalline silicon film and an oxide film sequentially, wherein the capacitor expansion oxide film on the upper portion of each transistor and the capacitor expansion oxide film are vertically etched on the polycrystalline silicon film, and the polycrystalline silicon film is isotropically etched to form a protrusion shape. Forming a contact between the transistor structures on the oxide contact oxide film; depositing a polysilicon film for a storage node as a whole along the curved shape, and then applying a photoresist to the oxide expansion film; Will be revealed Etching until the capacitor expansion oxide film is wet-etched; depositing the capacitor dielectric film and the polycrystalline silicon film for the plate in order and removing unnecessary portions.

In addition, the present invention provides a stacked capacitor having protrusions at each storage node on each gate located in the field region and the active region, wherein the protrusions are trenched to have a puddle shape in which the capacitor area is expanded. It includes.

This will be described in detail with reference to the attached second drawings (a) to (o) as follows.

First, as shown in FIG. 2A, the field oxide film 2 is formed on the substrate 1 by the conventional LOCOS process to define the field region and the active region, and then the gate oxide film 3 is formed.

In order to form a transistor as shown in FIG. 2B, the gate polycrystalline silicon film 4 and the gate cap oxide film 5 are sequentially formed in turn, and the gate is limited using the photosensitive agent PR ₁ as shown in FIG. 2C. Likewise, unnecessary portions are removed to form the gate oxide film 3a, the polysilicon gate 4a, and the gate cap oxide film 5a.

Thereafter, using the gate as a mask and forming a low concentration source and a drain region by low concentration ion implantation, the photoresist for limiting gate PR ₁ is removed as shown in FIG. 2e and then the oxide film 6 for sidewall oxide film as in FIG. 2f is deposited. The RIE is etched to form the sidewall oxide film 6a as shown in FIG. 2G to form a word line by completing transistors in the field region and the active region, respectively.

A high concentration source and drain ions are implanted to form a source and drain junction (not shown) of the LDD structure.

Subsequently, as shown in FIG. 2h, an oxide film 7 for etch contact etch, an undoped polysilicon film 8 having a thickness of about 3000 Å-6000 과 and an oxide film 9 having a thickness of about 2000-6000 과 are formed in order. As shown in Fig. 2i, a portion of the polysilicon film 8 and the oxide film 9 in which the field region is located above each transistor in the active region so as to be self-matched is defined using a photosensitive agent PR ₂ . It is etched flexibly with the 2j tile.

At this time, the upper oxide film 9 is dry etched vertically with respect to the surface of the substrate 1 and the lower polysilicon film 8 is about 1000-3000 mm thick using SF ₆ GAs or Cl ₂ + SF ₆ GAs. Isotropically etched to form a bend.

The isotropic etch can be made by vertical etch with dry etch followed by etch again with wet etch.

Subsequently, as shown in FIG. 2k, the photoresist PR ₃ is used to define the mem contact, and the oxide film 7 is etched to form the mem contact, and then a thermally oxidized film (not shown) is formed to a thickness of about 100-500 kPa.

As shown in FIG. 2L, the polysilicon film 10 for the storage node has a thickness of about 500-2500 kPa along the open contact with the oxide film 7 and the bend of the bent polycrystalline silicon film 8 and the oxide film 9. Deposit.

And applies a photosensitive material (PR ₄₎ as a whole, such as to help the 2m and a photosensitive agent (PR _4), and the ratio of first etch rate in the storage node polysilicon layer (10): 1 or 2: set to 1 degree, and then the post-processing etch (Etch Back)

In this case, the etch degree may expose the surface of the capacitor expansion oxide film 9 to the polysilicon film 10 for the storage node surrounding the capacitor expansion oxide film 9.

When the post-treatment etch finishes as described above, the surface of the capacitor-extended oxide film 9 is removed by wet etching, as shown in 2n, and then the photoresist PR ₄ is removed.

Here, the wet etch thickness of the oxide film 9 is obtained by adding about 2000 kPa to the deposition thickness.

Subsequently, the capacitor dielectric layer 11 is deposited using the ONO layer, the NO layer, or Ta ₂ O ₅ along the curvature of the polysilicon layer 10 for the storage node, and the doped polysilicon layer (In −) is doped. A self-matching multilayer capacitor is manufactured by depositing Situ Doped Polysi) or a polycrystalline silicon film and then forming a polysilicon film 12 for the plate of the capacitor to a thickness of about 1000-3000 Å.

As described above, the present invention has the following effects.

First, it is possible to improve the recharging characteristics of the device by increasing the capacitance of the capacitor under the same area of integration.

Second, the use of self-matching process can increase the process efficiency, and can also improve the characteristics of the product.

Claims (5)

A stacked capacitor having protrusions on each of the storage nodes on the gates of the feed region and the active region, wherein each of the protrusions has a trench shape in which the capacitor area is extended. The oxide film 7 and the capacitor for etch contact on the substrate are formed as a whole on the substrate on which the transistor is formed by forming a field region and an active region on a substrate and a transistor having a gate having sidewall spacers and an impurity region having source and drain functions. Forming an undoped polycrystalline silicon film 8 and an oxide film 9 in turn, and forming a mask on the capacitor expansion oxide film 9 above the gate of the film transistor to etch the capacitor expansion oxide film 9 vertically. Forming the protrusions by isotropically etching the polycrystalline silicon film 8, removing the mask, and selectively removing the oxide film 7 for etch contact etching to form a buried contact in an impurity region of each transistor, After depositing the polycrystalline silicon film 10 for the storage node as a whole along the curved shape For (PR _4), the coating and these in until after reveal the said capacitor expansion oxide film 9 for a chibeop the treatment PL step, removing the photosensitive material (PR _4), and the capacitor extension oxide film 9 is chibeop wet And removing the capacitor dielectric film (11) and the plate polycrystalline silicon film (12) in order and removing unnecessary portions in order. The method of claim 2, wherein the isotropic etching of the undoped polycrystalline silicon film (8) is performed using SF ₆ or Cl ₂ + SF ₆ gas. 3. The method of claim 2, wherein the isotropic etch process comprises a step of vertical etching by dry etching followed by wet etching. 3. The method of claim 2, wherein a thermally oxidized film is formed to a thickness of about 100-500 kV before deposition of the polycrystalline silicon film (10) for the storage node.