KR930009128B1 - Structure of trench type dram cell and fabricating method thereof - Google Patents

Abstract

The method for manufacturing a DRAM cell of SPT (Substrate Plate Trench) type forms a polysilicon column in the trench to expand cell capacitance. The method includes the steps of: forming trenches in the portion except the active region to deposit highly concentrated impurity poly to form poly-1 and coat SOG (Spin On Glass): etching the high concentration impurity poly and poly-1 to produce a circular poly column in the trench and execute a thin oxidation on the remaining poly on the bottom of the trench; wet-etching the oxide to deposite poly-2; removing the high temperature oxide layer and poly-2 to deposit a node poly and etch it with a node mask; and depositing a high temperature oxide layer

Description

Trench type DRAM cell manufacturing method and structure

1 is a process flow diagram of a conventional trench type dream cell.

2 is a process flow diagram of a trench type DRAM cell of the present invention.

* Explanation of symbols for main parts of the drawings

1: P-type silicon substrate 2: P- epi layer

3: field oxide 4: gate poly

5: word line 6: high temperature oxide film

7: trench 8: P + poly

9: poly-1 10: SOG

11: round poly column 13: poly-2

14: node-poly 15: node-mask

16: high temperature oxide film + BPSG 17: bit line

18: void

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a substrate plate (SPT) type DRAM cell, and more particularly, to a method and structure for manufacturing a trench type DRAM cell of a circular column suitable for forming a polysilicon column in a trench to increase the capacitance of the cell. It is about.

The prior art configuration is to trench isolation 21, dig a trench for capacitor formation, form dielectric layer 22, deposit poly 23 and etch back to form storage electrodes as shown in FIG. Deposition of poly (25) again, node is made using node mast, ion implantation of n + (26) in poly (25) and silicon (20) year, isolating node and making moss in active area and BPSG After depositing (27), a contact is formed and a bit line 28 is made.

Also, as shown in FIG. 1A, a trench is dug in the substrate 30, the dielectric layer 31 is formed, and the poly 32 is deposited to form a storage node, and the field oxide 33 is grown using a LOCOS process. (34), ion implantation of P + (35), deposition of poly (36), connection of nodes with P + (35) using a node mask, and formation of bit lines (37) after isolation.

However, in the conventional trench type DRAM cell, there is a problem in that sufficient capacitance required in the memory cell cannot be obtained.

Accordingly, the present invention is to solve the above problems, as shown in Figures 2a to b to grow a P- epi layer on the P-type silicon substrate 1 to grow the field oxide (3), high concentration After the impurity ion implantation, the gate poly (4) and the word line (5) are formed, a mask is used for the portion excluding the active region of the MOS TR completed by depositing the high temperature oxide film (6). To form the trenches 7.

After depositing a high concentration impurity poly (N +, P +) (8) in the trench (7) and etching back to form a poly-1 (9) and then coating a SOG (Spin ON Glass) (10) Coating) to etch back process.

After the above process, as shown in Figs. 2C to D, high concentration impurity poly (N +, P +) (8) is etched with RIE gas to form a circular polycolumn 11 in the trench 7, and the bottom of the trench 7 is formed. After oxidizing the remaining poly (12) thinly (Oxidation), the oxide film is removed by wet etch (wet etch) to deposit the poly-2 (13). At this time, even if a void 18 is generated in the poly-2 14, there is no problem. After the process, as shown in FIGS. 2e to f, the high temperature oxide film G and the poly-2 (13) are removed by RIE technology, and then the node poly 14 is deposited. The node-mask 15 is used to etch.

As a final process, the high temperature oxide film + BPSG 16 is deposited as shown in FIG. 2G, and then a metal for the bit line is deposited on the contact to form the bit line 17.

As described above, the SPT-type DRAM cell manufacturing method of the present invention has a polysilicon circular pillar in the trench, so that the capacitance of the cell is increased and the residual poly (12) is oxidized to wet etch to form the circular poly pillar 11. It has the effect of reducing the damage that occurs.

Claims (8)

Forming a trench in the portion except the active region, depositing a high concentration of impurity poly, forming a poly-1, coating a SOG, and etching a high concentration of impurity poly and poly-1 to form a circular poly pillar in the trench Oxidation process, Oxidation of the remaining poly at the bottom of the trench, followed by wet etching to remove poly-2 and depositing poly-2, RIE technology to remove the high temperature oxide film and poly-2 to deposit node-poly And a process of etching using a node-mask, and forming a bit line by depositing a high temperature oxide film + BPSG and depositing a metal for the bit line in the contact. Type DRAM cell manufacturing method. A trench-type DRAM cell structure, characterized in that the capacitance of the cell is increased by forming a polysilicon circular pillar after making the trench. The method of manufacturing a trench type DRAM cell of claim 1, wherein P + is used as a high concentration impurity in the trench. 2. The method of claim 1, wherein n + is used as a high concentration impurity in the trench. 2. The method of claim 1, wherein the poly-1 is doped with impurities. The method of claim 1, wherein the poly-1 is a doped trench type DRAM cell manufacturing method characterized in that the impurities doped. 2. The method of claim 1, wherein the poly-2 is doped with impurities. The method of claim 1, wherein the node-poly is a doped trench type DRAM cell manufacturing method characterized in that the impurity doped.

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