KR930008961A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

Info

Publication number
KR930008961A
KR930008961A KR1019910019211A KR910019211A KR930008961A KR 930008961 A KR930008961 A KR 930008961A KR 1019910019211 A KR1019910019211 A KR 1019910019211A KR 910019211 A KR910019211 A KR 910019211A KR 930008961 A KR930008961 A KR 930008961A
Authority
KR
South Korea
Prior art keywords
ion implantation
semiconductor device
manufacturing
dose
inclination
Prior art date
Application number
KR1019910019211A
Other languages
Korean (ko)
Other versions
KR950002183B1 (en
Inventor
홍승우
김병기
장윤기
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910019211A priority Critical patent/KR950002183B1/en
Publication of KR930008961A publication Critical patent/KR930008961A/en
Application granted granted Critical
Publication of KR950002183B1 publication Critical patent/KR950002183B1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체장치에 제조공정중 이온주입기술에 관한 것으로, 고집적 반도체 디바이스의 불순물영역형성을 위한 이온주입방법에 있어서, 도우즈량을 적게하여 7°경사로 이온주입하는 제1단계와 도우즈량을 많게 하여 0°경사로 이온주입하는 제2단계로 이루어진 것을 특징으로 하는 본 발명에 의하면, 종래의 이온주입기술의 문제점인 쉐도윙효과, 측면확산 및 채널링현상을 방지 또는 감소시킬 수 있음에 따라 반도체 메모리소자 제조에 적용했을 경우 소자의 전기적 특성 개선에 기여할 수 있게 된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ion implantation technique during a manufacturing process in a semiconductor device. In the ion implantation method for forming an impurity region of a highly integrated semiconductor device, the first step of reducing the dose and ion implanting at a 7 ° inclination is increased. According to the present invention, the second step of ion implantation at an inclination of 0 °, the semiconductor memory device according to the present invention can prevent or reduce the shadowing effect, side diffusion and channeling phenomena of the conventional ion implantation technology. When applied to manufacturing, it can contribute to the improvement of the electrical characteristics of the device.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1A도 (a), (b) 및 제1B도는 본 발명에 의한 이온주입방법을 설명하기 위한 도면.1A, 1A, 1B and 1B are views for explaining the ion implantation method according to the present invention.

Claims (5)

고집적 반도체 디바이스의 불순물영역형성을 위한 이온주입방법에 있어서, 도우즈량을 적게하여 7°경사로 이온주입하는 제1단계와 도우즈량을 많게 하여 0°경사로 이온주입하는 제2단계로 이루어진 것을 특징으로 하는 반도체장치의 제조방법.An ion implantation method for forming an impurity region in a highly integrated semiconductor device, comprising: a first step of ion implantation at a 7 ° inclination with a small dose and a second step of ion implantation at a 0 ° inclination with a large dose Method of manufacturing a semiconductor device. 제1항에 있서, 상기 제1단계 이온주입공정시 반도체 메모리 셀내의 게이트라인과 평행한 주사빔을 이용하여 이온을 주입하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein in the first step ion implantation process, ions are implanted using a scanning beam parallel to a gate line in a semiconductor memory cell. 제1항에 있어서, 상기 제1단계 이온주입시의 도우즈량은 1×1014~5×1014ions/㎠인 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the dose in the first step ion implantation is 1 × 10 14 to 5 × 10 14 ions / cm 2. 제1항에 있어서, 상기 제2단계 이온주입시의 도우즈량은 1×1015~5×1016ions/㎠인 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the dose amount during the second stage ion implantation is 1 × 10 15 to 5 × 10 16 ions / cm 2. 제1항에 있어서, 상기 제1단계 이온주입을 도우즈량을 1/2로 나누고 각도를 변화시켜 2회에 걸쳐 행하는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first stage ion implantation is performed twice by dividing the dose by 1/2 and changing the angle. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910019211A 1991-10-30 1991-10-30 Manufacturing method for semiconductor device KR950002183B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910019211A KR950002183B1 (en) 1991-10-30 1991-10-30 Manufacturing method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910019211A KR950002183B1 (en) 1991-10-30 1991-10-30 Manufacturing method for semiconductor device

Publications (2)

Publication Number Publication Date
KR930008961A true KR930008961A (en) 1993-05-22
KR950002183B1 KR950002183B1 (en) 1995-03-14

Family

ID=19322018

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910019211A KR950002183B1 (en) 1991-10-30 1991-10-30 Manufacturing method for semiconductor device

Country Status (1)

Country Link
KR (1) KR950002183B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451469B1 (en) * 2001-12-29 2004-10-08 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451469B1 (en) * 2001-12-29 2004-10-08 주식회사 하이닉스반도체 Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
KR950002183B1 (en) 1995-03-14

Similar Documents

Publication Publication Date Title
KR920017245A (en) Semiconductor device and manufacturing method thereof
US5770502A (en) Method of forming a junction in a flash EEPROM cell by tilt angle implanting
KR970013412A (en) Manufacturing method of semiconductor device
US5134447A (en) Neutral impurities to increase lifetime of operation of semiconductor devices
EP0471131B1 (en) Process for obtaining an N-channel single polysilicon level EPROM cell
KR950034738A (en) Structure and manufacturing method of thin film transistor
KR930008961A (en) Manufacturing Method of Semiconductor Device
KR100233558B1 (en) Manufacturing method of a semiconductor device
WO2002037552A3 (en) Doping for flash memory cell
KR20010039227A (en) Thin film transistor and fabricating mathod thereof
KR19980027761A (en) Multiple pocket implants for improved MOSFET and channel length control
KR940016609A (en) Method for manufacturing N-type transistor implanted with fluorine ion
KR960009015A (en) Gate electrode formation method of semiconductor device
KR20050066901A (en) Mos transistor having low junction capacitance and method for fabricating the same
KR950002184B1 (en) Manufacturing method for semiconductor memory device
KR970054446A (en) Semiconductor device and manufacturing method
KR100250685B1 (en) Manufacturing method of a transistor for dram
KR20040006772A (en) Method for fabricating semiconductor device
KR950034737A (en) Structure and manufacturing method of thin film transistor
KR950010126A (en) Method for forming source / drain junction of semiconductor device
KR940027064A (en) Ultrafine junction formation method by multiple low energy ion implantation
KR960039401A (en) Mask ROM Manufacturing Method
KR960019773A (en) Structure and manufacturing method of thin film transistor
KR970003773A (en) Semiconductor device manufacturing method
KR950004576A (en) Method of forming threshold voltage control layer of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010215

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee