KR930008526B1 - Method for fabricating smeiconductor divice - Google Patents
Method for fabricating smeiconductor divice Download PDFInfo
- Publication number
- KR930008526B1 KR930008526B1 KR1019900016302A KR900016302A KR930008526B1 KR 930008526 B1 KR930008526 B1 KR 930008526B1 KR 1019900016302 A KR1019900016302 A KR 1019900016302A KR 900016302 A KR900016302 A KR 900016302A KR 930008526 B1 KR930008526 B1 KR 930008526B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- insulating film
- capacitor
- etching
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract 2
- 238000001039 wet etching Methods 0.000 claims abstract 2
- 239000004952 Polyamide Substances 0.000 claims description 5
- 229920002647 polyamide Polymers 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000007796 conventional method Methods 0.000 claims 1
- 238000005452 bending Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
제 1 도는 종래의 공정단면도.1 is a conventional process cross-sectional view.
제 2 도는 본 발명의 공정단면도.2 is a cross-sectional view of the process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 필드산화막1 substrate 2 field oxide film
3 : 게이트산화막 4 : 게이트전극3: gate oxide film 4: gate electrode
5 : 게이트 캡산화막 5a : 게이트 측벽산회막5 gate cap oxide film 5a gate sidewall diffusion film
6 : 폴리마이드막 7 : 산화막6: polyamide film 7: oxide film
8 : 스토리지노드 폴리실리콘막 9 : 커패시터 유전체막8: storage node polysilicon film 9: capacitor dielectric film
10 : 플레이트 폴리실리콘막 11 : 절연막10 plate polysilicon film 11 insulating film
12 : 비트라인12: bit line
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 복수의 절연막으로 구성된 절연스택(Stack)을 건식 및 습식으로 부분에치하여 형성된 굴곡표면을 커패시터 면적으로 이용하므로써 축전용량을 증가시킬 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, by using a curved surface formed by partially and partially insulating an insulating stack composed of a plurality of insulating films to increase the capacitance.
종래의 트렌치드 앤드 새들드(Trenched and Saddled) 스택 커패시터 셀 제조공정을 첨부된 제 1a 도 내지 (g) 도를 참조하여 설명하면 다음과 같다.A process of fabricating a conventional trenched and saddled stack capacitor cell will now be described with reference to FIGS. 1A through 1G.
먼저 (a)와 같이 P형 기판(20) 위에 소오스 및 드레인 접합과 절연산화막(21), 게이트 산화막(22) 및 게이트 폴리실리콘(23)을 형성한 후 단차를 형성하기 위해 스택 폴리실리콘(24)을 형성한다.First, as shown in (a), the source and drain junctions, the insulating oxide layer 21, the gate oxide layer 22, and the gate polysilicon 23 are formed on the P-type substrate 20, and then the stacked polysilicon 24 is formed to form a step. ).
이어 (b)와 같이 P형 패터닝(Patterning) 공정을 거쳐 새들패턴을 형성하고 (c)와 같이 메몰 콘택에치를 행한 다음 (d)와 같이 스토리지 노드 폴리실리콘(25)을 형성한다. 그리고 (e)와 같이 상기 스토리지 노드 폴리실리콘(25)을 패터닝한 후 커패시터 절연막(26)을 형성한다.Subsequently, a saddle pattern is formed through a P-type patterning process as shown in (b), a etch contact etch is performed as shown in (c), and then a storage node polysilicon 25 is formed as shown in (d). After the patterning of the storage node polysilicon 25 as shown in (e), the capacitor insulating film 26 is formed.
이어 (f)와 같이 플레이트 폴리실리콘(27)을 형성하고 마지막으로 (g)와 같이 그위에 절연막(28)을 형성한 다음 비트라인(29)을 형성하므로써 셀을 완성하게 된다.Subsequently, the plate polysilicon 27 is formed as shown in (f) and the insulating film 28 is formed thereon as shown in (g), and then the bit line 29 is formed to complete the cell.
그러나 상기 종래 기술은 제 1c 도의 메몰 콘택 에치를 할 시 에스펙트 비(Aspect Ratio)가 한계가 있으므로 커패시터 단차를 주기 위한 스택 폴리실리콘(24)의 두께가 제한되어 커패시터 면적을 증가시키는데 한계가 있었다.However, since the aspect ratio of the prior art when the etch contact etch of FIG. 1c is limited, the thickness of the stacked polysilicon 24 for giving the capacitor step is limited, thereby increasing the capacitor area.
본 발명은 상기 단점을 제거키 위한 것으로 커패시터 면적을 증가시켜 축전용량을 증대시킬 수 있는 방법을 제공하는데 그 목적이 있다.The present invention aims to eliminate the above disadvantages, and an object thereof is to provide a method for increasing capacitance by increasing a capacitor area.
상기 목적을 달성하기 위해 본 발명은 패스(pass) 트랜지스터와 커패시터로 구성되는 메모리 셀 제조공정에 있어서, 복수의 절연막으로 구성된 절연 스택을 부분식각하여 형성된 굴곡면에 스토리지 노드 폴리실리콘막을 형성하므로써 커패시터 면적을 늘리도록 한다.In order to achieve the above object, the present invention provides a capacitor area by forming a storage node polysilicon film on a curved surface formed by partially etching an insulating stack composed of a plurality of insulating films in a memory cell manufacturing process consisting of a pass transistor and a capacitor. Increase the
이를 첨부된 제 2a 내지 d 도를 참조하여 상술하면 다음과 같다.This will be described below with reference to the accompanying drawings 2a to d as follows.
먼저 (a)와 같이 기판(1)위의 소정부분에 필드산화막(2)을 형성하고, 통상의 공정에 의해 게이트 산화막(3), 그 상부에 게이트 캡 산화막(5)이 형성되고 그 측면에 게이트 측벽산화막(5a)이 형성된 게이트 전극(4)과 소오스 및 드레인영역(S/D)으로 이루어지는 트랜지스터를 형성한 후 결과물상에 제 1 절연막으로서, 예컨대 폴리마이드막(6)과 제 2 절연막으로서, 예컨대 산화막(또는 질화막)(7)을 차례로 형성하여 스택구조 절연막을 형성한다.First, as in (a), a field oxide film 2 is formed on a predetermined portion on the substrate 1, and a gate oxide film 3 and a gate cap oxide film 5 are formed on the side thereof by a conventional process. After forming a transistor comprising a gate electrode 4 having a gate sidewall oxide film 5a formed thereon and a source and drain region S / D, the first insulating film is formed as a first insulating film, for example, as a polyamide film 6 and a second insulating film. For example, an oxide film (or nitride film) 7 is sequentially formed to form a stack structure insulating film.
이어 (b)와 같이 상기 산화막(또는 질화막)(7)을 소정부분 건식 식각에 의해 제거하여 개구부를 형성한 다음 상기 개구부가 형성된 산화막(7)을 마스크로 이용하여 그 하층의 폴리마이드막(6)을 식각하여 기판부분(소오스 또는 드레인영역)을 노출시킨 후 결과물 전면에 스토리지 노드 폴리실리콘막(8)을 형성한다.Subsequently, as shown in (b), the oxide film (or nitride film) 7 is removed by dry etching to form an opening, and then the polyamide film 6 of the lower layer is formed using the oxide film 7 having the opening as a mask. ) Is exposed to expose the substrate portion (source or drain region), and then the storage node polysilicon film 8 is formed on the entire surface of the resultant.
그리고 나서 (c)와 같이 상기 스토리지 노드 폴리실리콘막(8)을 스토리지 노드 패턴으로 패터닝하여 커패시터 스토리지 노드(8)을 형성한 다음 폴리마이드막(6)과 산화막(7)을 차례로 습식 에치하여 제거하므로써 많은 굴곡이 이루어지도록 한다. 그리고 (d)와 같이 상기 스토리지 노드(8) 표면에 커패시터 유전체막(9)을 형성하고, 이 유전체막(9)상에 플레이트 폴리실리콘막(10)을 형성하고 이를 소정 패턴으로 패터닝하여 커패시터 플레이트 전극(10)을 형성한 다음 결과물 전면에 절연막(11)을 형성한다.Then, as shown in (c), the storage node polysilicon layer 8 is patterned into a storage node pattern to form a capacitor storage node 8, and then the polyamide layer 6 and the oxide layer 7 are wet-etched and removed in turn. This allows a lot of bending. As shown in (d), a capacitor dielectric layer 9 is formed on the surface of the storage node 8, and a plate polysilicon layer 10 is formed on the dielectric layer 9 and patterned in a predetermined pattern to form a capacitor plate. After the electrode 10 is formed, an insulating film 11 is formed on the entire surface of the resultant.
이어 상기 절연막(11)의 소정 부위에 비트라인 콘텍트 개구부를 형성하고 결과물상에 비트라인(12)을 형성하므로써 공정이 완료된다.Subsequently, the process is completed by forming bit line contact openings in predetermined portions of the insulating film 11 and forming bit lines 12 on the resultant.
이상과 같이 본 발명에 의하면 복수의 절연막으로 구성된 스택구조의 절연막을 여러번 부분습식 에치하여 많은 굴곡이 이루어지게 하고 이위에 스토리지 노드 풀리실리콘막(8)을 형성하므로써 커패시터 면적이 증가되고 이에 따른 축전용량이 증대되는 효과가 있다.As described above, according to the present invention, the partial insulation of the stack structure of the plurality of insulating films is partially wet-etched to allow a large amount of bending, and the capacitor area is increased by forming the storage node pulley silicon film 8 thereon. This has the effect of increasing.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900016302A KR930008526B1 (en) | 1990-10-15 | 1990-10-15 | Method for fabricating smeiconductor divice |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900016302A KR930008526B1 (en) | 1990-10-15 | 1990-10-15 | Method for fabricating smeiconductor divice |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920008924A KR920008924A (en) | 1992-05-28 |
| KR930008526B1 true KR930008526B1 (en) | 1993-09-09 |
Family
ID=19304655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900016302A KR930008526B1 (en) | 1990-10-15 | 1990-10-15 | Method for fabricating smeiconductor divice |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930008526B1 (en) |
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1990
- 1990-10-15 KR KR1019900016302A patent/KR930008526B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920008924A (en) | 1992-05-28 |
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