KR930008015B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device of DRAM memory cell comprising a transistor and a capacitor, is prepared by (1) forming a field oxide on a region, and a trench on a region to be a bit line and a gate, by forming a well on a substrate, (2) forming a gate by deposition of a polysilicon on both the sides of trench, and by RIE, (3) forming a common source/drain and another source/drain between the field oxide film and the trench, (4) depositing an insulation film on all surface, forming a contact by etching the source/drain region and forming a bit line on the contact, (5) depositing an insulation film on all surface, forming a contact by etching the another source/drain region and forming a storage electrode on the contact, and (6) forming a dielectric film and a plate electrode on the storage electrode.

Description

Manufacturing method of semiconductor device

1 is a manufacturing process diagram of a conventional semiconductor device.

2 is a manufacturing process diagram of a semiconductor device of the present invention.

* Explanation of symbols for main parts of the drawings

1: silicon substrate 2: well

3: field oxide film 4: gate oxide film

5 gate 6 capgate oxide film

7: oxide film for gate insulation 8: polysilicon

9: silicon tungsten 10: bit line and node isolation oxide film

11: storage node polysilicon 12: ONO

13: Plate Polysilicon

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, in which step coverage and capacitor area are increased to be particularly suitable for ultra high integration devices. Conventional cell fabrication method uses a multilayer or trench method to satisfy capacitance on a narrow area required for high grade devices. As a result of having a high lamination structure, step coverage is deteriorated, which causes difficulties in post-processing.

A general method of manufacturing a double node capacitor cell in a semiconductor device manufacturing process is the same as that of FIG. In other words, the well 2 is formed on the silicon substrate 1 as shown in FIG. 1a, the field oxide film 3 is formed by local oxide deposition, and then ion implanted into a channel for depositing the first gate oxide and controlling the threshold voltage as shown in FIG. 1b. After the first gate oxide film is removed, the first gate oxide film 4 is grown, the polysilicon deposition and the cap gate oxide film 6 are applied to form the gate 5 by a mask and an etching process, and the sidewalls after n ^- impurity ion implantation are implanted. (13) is formed to form a source / drain of LDD structure by n ⁺ impurity ion implantation.

Then, as shown in FIG. 1C, the oxide layer 7, which is a gate insulating layer, is deposited, the primary storage node polysilicon 14 is deposited, and a buried contact is formed to deposit a mask in a state in which the secondary storage node polysilicon 15 is deposited. Eliminate unnecessary parts by process and etching.

Thereafter, ONO (oxide / nitride / oxide) 12, which is a dielectric film, is coated as shown in FIG. 1D, and plate polysilicon 13 is deposited and patterned. Then, for isolation between the bit line and plate polysilicon 13 as shown in FIG. The semiconductor device is fabricated by applying the oxide film 16 and applying the BPSG 17 to improve step coverage when forming the bit line, forming a metal contact (bit line contact), and applying the metal 18.

However, such a conventional method of manufacturing a semiconductor device is difficult to satisfy a large capacitance in a small area required by a high density device when the multilayer capacitor method is used, and has a higher stacking structure to satisfy the same condition, which results in poor step coverage. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a method for manufacturing a semiconductor device, which is suitable for highly integrated devices by improving step coverage and increasing capacitor area by forming sidewall gates and buried bitlines.

The present invention for achieving this object is described with reference to FIG. 2 as follows. First, as shown in FIG. 2A, the wells 2 are formed in the silicon substrate 1 to form trenches in a region where bit lines and gates are to be formed by a masking and etching process, and a field oxide film 3 is formed by a local oxide film deposition method.

Then, as shown in Fig. 2b, after the ion implantation into the channel region for the first gate oxide film deposition and the threshold voltage control, the first gate oxide film is removed and the gate oxide film 4 is grown on both sidewalls of the trench to deposit polysilicon as a gate. After forming the sidewall gate (5) with the Sting and Reactive Ion Eton (RIE), the cap gate oxide film 6 is applied and then RIE is formed to form the sidewall cap gate oxide film. And another source / drain are formed between and the field oxide film 3.

Then, as shown in FIG. 2C, an oxide film 7 is deposited on the entire surface for isolation of the gate 4 and the source / drain and bit lines, and the oxide film 7 formed in the common source / drain region is removed by masking and cutting. After forming the bit line contact, the polysilicon 8 is deposited to etch back, and the bit line is formed by two masking and etching on which the silicon tungsten 9 is deposited.

Next, as shown in FIG. 2D, an oxide layer 10 is deposited on the entire surface for isolation of the bit line and the node polysilicon, and a capacitor buried contact is formed for the node polysilicon junction, and then the node polysilicon 11 is deposited and masked. Storage nodes are defined by etch and etching. In this case, in-situ doped amorphous silicon may be used as a material for forming the storage node.

The semiconductor device of the present invention is manufactured by coating ONO 12 as a dielectric film, depositing plate polysilicon 13, and defining a plate by masking and etching as shown in FIG.

As described above, the present invention can reduce the cell area while forming the active area length by forming the sidewall gates 5, form a self-aligned gate, and improve step coverage by forming buried bit lines. It works.

In addition, since the node is formed up to the bit line contact region, the capacitance of the double node can be obtained with only a single node.

Claims (3)

In a memory cell of a DRAM having one transistor and one capacitor, a well 2 is formed in a silicon substrate 1 to form a field oxide film 3 in a trench and a predetermined portion in a portion where a bit line and a gate are to be formed. Forming a gate, forming a gate 5 by depositing polysilicon on both sides of the trench and RIE, forming a common source / drain between the gate 5, and forming a field oxide film 3 and a trench Forming another source / drain between the same; and depositing an insulating film 7 on the entire surface, and then etching the insulating film 7 to be formed in the common source / drain region to form a contact, and forming a bit line on the contact portion. Forming a storage electrode 11 on the contact portion by etching the insulating film 10 to be formed on another source / drain region after depositing the insulating film 10 on the entire surface; On the storage electrode Conductor film manufacturing method of the semiconductor element in the step of forming the 12 and the plate electrode 13. The method of claim 1, wherein the semiconductor device is made of amorphous silicon in-situ-doped with a material forming a storage node. 2. A method according to claim 1, wherein the bit lines are formed in the trench with polysilicon (8) and silicon tungsten (9).