KR930008015B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR930008015B1 KR930008015B1 KR1019910011716A KR910011716A KR930008015B1 KR 930008015 B1 KR930008015 B1 KR 930008015B1 KR 1019910011716 A KR1019910011716 A KR 1019910011716A KR 910011716 A KR910011716 A KR 910011716A KR 930008015 B1 KR930008015 B1 KR 930008015B1
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- gate
- trench
- oxide film
- drain
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000003860 storage Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000009271 trench method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제 1 도는 종래의 반도체 소자의 제조공정도.1 is a manufacturing process diagram of a conventional semiconductor device.
제 2 도는 본 발명의 반도체 소자의 제조공정도.2 is a manufacturing process diagram of a semiconductor device of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘기판 2 : 웰1: silicon substrate 2: well
3 : 필드산화막 4 : 게이트산화막3: field oxide film 4: gate oxide film
5 : 게이트 6 : 캡게이트산화막5 gate 6 capgate oxide film
7 : 게이트 절연용산화막 8 : 폴리실리콘7: oxide film for gate insulation 8: polysilicon
9 : 실리콘텅스텐 10 : 비트라인과 노드간격리산화막9: silicon tungsten 10: bit line and node isolation oxide film
11 : 스토리지 노드 폴리 실리콘 12 : ONO11: storage node polysilicon 12: ONO
13 : 플레이트 폴리실리콘13: Plate Polysilicon
본 발명은 반도체 소자 제조방법에 관한 것으로 특히 초고집적 소자에 적당하도록 스텝 커버리지와 커패시터 면적을 증가한 것이다. 종래의 셀 제조방법으로는 하이 그레이드(High Grade) 소자에서 요구하는 좁은 면적상에 커패시턴스를 만족시키기 위해 적층형이나 트랜치 방식을 사용하고 있으나 트랜치 커패시터 방식을 그 제조방법의 복잡성에 문제가 있고 적층형 커패시터 방식은 높은 적층구조를 가짐으로써 스텝 커버리지가 나빠져 후공정에 어려움을 야기시키고 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a semiconductor device, in which step coverage and capacitor area are increased to be particularly suitable for ultra high integration devices. Conventional cell fabrication method uses a multilayer or trench method to satisfy capacitance on a narrow area required for high grade devices. As a result of having a high lamination structure, step coverage is deteriorated, which causes difficulties in post-processing.
반도체 소자 제조공정중 일반적인 이중 노드 커패시터 셀 제조방법은 제 1 도와 같다. 즉 제 1a 도와 같이 실리콘기판(1)에 웰(2)을 형성하고 국부산화막 증착법으로 필드산화막(3)을 형성한 다음 제 1b 도와 같이 제 1 게이트산화막 증착 및 임계전압 조절을 위한 채널에 이온주입하고 제 1 게이트 산화막을 제거한 다음 제 1 게이트산화막(4)을 성장시키고 폴리실리콘 증착과 캡 게이트 산화막(6)을 도포하여 마스크와 식각 공정으로 게이트(5)를 형성하고 n-불순물 이온주입후 측벽(13)을 형성하여 n+불순물 이온주입으로 LDD 구조의 소오스/드레인을 형성한다.A general method of manufacturing a double node capacitor cell in a semiconductor device manufacturing process is the same as that of FIG. In other words, the well 2 is formed on the silicon substrate 1 as shown in FIG. 1a, the field oxide film 3 is formed by local oxide deposition, and then ion implanted into a channel for depositing the first gate oxide and controlling the threshold voltage as shown in FIG. 1b. After the first gate oxide film is removed, the first gate oxide film 4 is grown, the polysilicon deposition and the cap gate oxide film 6 are applied to form the gate 5 by a mask and an etching process, and the sidewalls after n - impurity ion implantation are implanted. (13) is formed to form a source / drain of LDD structure by n + impurity ion implantation.
그리고 제 1c 도와 같이 게이트 절연층인 산화막(7)을 증착하고 1차 스토리지 노드 폴리실리콘(14)을 증착한 후 베리드 콘택을 형성하여 2차 스토리지 노드 폴리실리콘(15)을 증착한 상태에서 마스크 공정과 식각으로 불필요한 부분을 제거한다.Then, as shown in FIG. 1C, the oxide layer 7, which is a gate insulating layer, is deposited, the primary storage node polysilicon 14 is deposited, and a buried contact is formed to deposit a mask in a state in which the secondary storage node polysilicon 15 is deposited. Eliminate unnecessary parts by process and etching.
그후 제 1d 도와 같이 유전막인 ONO(산화막/질화막/산화막)(12)을 도포하고 플레이트 폴리실리콘(13)을 증착하여 패터닝한 뒤 제 1e 도와 같이 비트라인과 플레이트 폴리실리콘(13)간의 격리를 위해 산화막(16)을 도포하고 비트라인 형성시 스텝 커버리지 개선을 위해 BPSG(17)를 도포한후 금속콘택(비트라인 콘택)을 형성하고 금속(18)을 도포하여 반도체 소자를 제조한다.Thereafter, ONO (oxide / nitride / oxide) 12, which is a dielectric film, is coated as shown in FIG. 1D, and plate polysilicon 13 is deposited and patterned. Then, for isolation between the bit line and plate polysilicon 13 as shown in FIG. The semiconductor device is fabricated by applying the oxide film 16 and applying the BPSG 17 to improve step coverage when forming the bit line, forming a metal contact (bit line contact), and applying the metal 18.
그러나 이와같은 종래의 반도체 소자 제조방법은 적층형 커패시터 방식을 사용한 경우 고집적 소자에서 요구되는 좁은 면적에서 큰 커패시턴스를 만족하기 어려우며 동조건을 만족하기 위해서는 더 높은 적층구조를 갖어야 되는데 이렇게 되면 스텝 커버리지가 불량하게 되는 문제점이 있다.However, such a conventional method of manufacturing a semiconductor device is difficult to satisfy a large capacitance in a small area required by a high density device when the multilayer capacitor method is used, and has a higher stacking structure to satisfy the same condition, which results in poor step coverage. There is a problem.
본 발명은 이와같은 문제점을 해결하기 위한 것으로 본 발명의 목적은 측벽 게이트 형성과 베리드 비트라인 형성으로 스텝 커버리지 개선과 커패시터 면적을 증가시켜 고집적 소자에 적당하도록 한 반도체 소자 제조방법에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a method for manufacturing a semiconductor device, which is suitable for highly integrated devices by improving step coverage and increasing capacitor area by forming sidewall gates and buried bitlines.
이와같은 목적을 달성하기 위한 본 발명을 제 2 도를 이용하여 설명하면 다음과 같다. 우선 제 2a 도와 같이 실리콘기판(1)에 웰(2)을 형성하여 비트라인과 게이트가 형성될 영역에 마스킹과 식각공정으로 트랜치를 형성하고 국부산화막 증착법으로 필드산화막(3)을 형성한다.The present invention for achieving this object is described with reference to FIG. 2 as follows. First, as shown in FIG. 2A, the wells 2 are formed in the silicon substrate 1 to form trenches in a region where bit lines and gates are to be formed by a masking and etching process, and a field oxide film 3 is formed by a local oxide film deposition method.
그리고 제 2b 도와 같이 제일 게이트 산화막 증착과 임계전압 조절을 위한 채널 영역에 이온주입한 뒤 제일 게이트 산화막을 제거하고 트랜치의 양 측벽에 게이트산화막(4)을 성장시켜 게이트가 될 폴리실리콘을 증착하고 마스팅과 RIE(Reactive Ion Eton)로 측벽게이트(5)을 형성한 뒤 캡 게이트 산화막(6)을 도포하고 RIE하여 측벽 캡 게이트산화막을 형성한후 불순물 이온주입으로 게이트 사이에 공통 소오스/드레인과 트랜치와 필드산화막(3) 사이에 또 다른 소오스/드레인을 형성하다.Then, as shown in Fig. 2b, after the ion implantation into the channel region for the first gate oxide film deposition and the threshold voltage control, the first gate oxide film is removed and the gate oxide film 4 is grown on both sidewalls of the trench to deposit polysilicon as a gate. After forming the sidewall gate (5) with the Sting and Reactive Ion Eton (RIE), the cap gate oxide film 6 is applied and then RIE is formed to form the sidewall cap gate oxide film. And another source / drain are formed between and the field oxide film 3.
그후 제 2c 도와 같이 게이트(4)와 소오스/드레인 및 비트라인의 격리를 위해 산화막(7)을 전표면에 증착하고 마스킹과 삭각 공정으로 공통 소오스/드레인 영역에 형성된 산화막(7)을 제거하여 베리드 비트라인 콘택을 형성한 뒤 폴리실리콘(8)을 증착하여 에치백하고 실리콘텅스텐(9)을 증착한 두 마스킹과 식각으로 비트라인을 형성한다.Then, as shown in FIG. 2C, an oxide film 7 is deposited on the entire surface for isolation of the gate 4 and the source / drain and bit lines, and the oxide film 7 formed in the common source / drain region is removed by masking and cutting. After forming the bit line contact, the polysilicon 8 is deposited to etch back, and the bit line is formed by two masking and etching on which the silicon tungsten 9 is deposited.
그 다음 제 2d 도와 같이 비트라인과 노드 폴리실리콘의 격리를 위해 전표면에 산화막(10)을 증착하고 노드 폴리실리콘 접합을 위해 커패시터 베리드 콘택을 형성한 뒤 노드 폴리실리콘(11)을 증착하여 마스킹과 식각으로 스토리지 노드를 정의한다. 이때 스토리지 노드를 형성하는 물질로 인 시투(In-Situ)도핑된 비정질 실리콘을 사용할 수도 있다.Next, as shown in FIG. 2D, an oxide layer 10 is deposited on the entire surface for isolation of the bit line and the node polysilicon, and a capacitor buried contact is formed for the node polysilicon junction, and then the node polysilicon 11 is deposited and masked. Storage nodes are defined by etch and etching. In this case, in-situ doped amorphous silicon may be used as a material for forming the storage node.
제 2e 도와 같이 유전막인 ONO(12)를 도포하고 플레이트 폴리실리콘(13)을 증착하고 마스킹과 식각으로 플레이트를 정의하여 본 발명의 반도체 소자를 제조한다.The semiconductor device of the present invention is manufactured by coating ONO 12 as a dielectric film, depositing plate polysilicon 13, and defining a plate by masking and etching as shown in FIG.
이상에서 설명한 바와같이 본 발명은 측벽게이트(5)를 형성함으로써 액티브 영역길이를 같이하면서 셀 면적을 감소시킬 수 있고 셀프-얼라인 게이트를 형성할 수 있으며, 베리드 비트라인을 형성함으로써 스텝 커버리지 개선효과가 있다.As described above, the present invention can reduce the cell area while forming the active area length by forming the sidewall gates 5, form a self-aligned gate, and improve step coverage by forming buried bit lines. It works.
또한 비트라인 콘택 영역까지 노드를 형성함으로써 싱글 노드만으로도 더블 노드가 가지는 커패시턴스를 얻을 수 있는 효과가 있다.In addition, since the node is formed up to the bit line contact region, the capacitance of the double node can be obtained with only a single node.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011716A KR930008015B1 (en) | 1991-07-10 | 1991-07-10 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910011716A KR930008015B1 (en) | 1991-07-10 | 1991-07-10 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930003355A KR930003355A (en) | 1993-02-24 |
| KR930008015B1 true KR930008015B1 (en) | 1993-08-25 |
Family
ID=19317056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910011716A KR930008015B1 (en) | 1991-07-10 | 1991-07-10 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930008015B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100974729B1 (en) * | 2010-04-06 | 2010-08-06 | 주식회사신원 | Separating method of angora hair |
-
1991
- 1991-07-10 KR KR1019910011716A patent/KR930008015B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR930003355A (en) | 1993-02-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5312768A (en) | Integrated process for fabricating raised, source/drain, short-channel transistors | |
| US5492851A (en) | Method for fabricating attached capacitor cells in a semiconductor device having a thin film transistor | |
| US5290726A (en) | DRAM cells having stacked capacitors of fin structures and method of making thereof | |
| US7518198B2 (en) | Transistor and method for manufacturing the same | |
| US5470776A (en) | Method for fabricating stacked dynamic random access memory cell | |
| US5773330A (en) | Semiconductor device and method for fabricating the same | |
| US5317177A (en) | Semiconductor device and method of manufacturing the same | |
| US6661055B2 (en) | Transistor in semiconductor devices | |
| KR100545144B1 (en) | Reliable policide gate stack with reduced sheet resistance | |
| KR920010695B1 (en) | D-ram cell and its manufacturing method | |
| KR20000026967A (en) | Capacitor of semiconductor device and method for forming the same | |
| KR970000977B1 (en) | Capacitor producing method of semiconductor device | |
| KR930008015B1 (en) | Manufacturing method of semiconductor device | |
| KR960005249B1 (en) | Dram manufacture method | |
| KR930005234B1 (en) | Cell manufacture method of fin-stack cell | |
| KR940009631B1 (en) | Manufacturing method of dram with trench capacitor | |
| US20230178645A1 (en) | Semiconductor structure and method for forming same | |
| US20080057660A1 (en) | Step-gate for a semiconductor device | |
| US12027207B2 (en) | Vertical memory devices and methods for operating the same | |
| US20230189516A1 (en) | Vertical memory devices and methods for forming the same | |
| KR20000013402A (en) | Fabrication method of memory capacitor | |
| KR920008294B1 (en) | Method of manufacturing for semiconductor device | |
| GB2293691A (en) | Semiconductor memory devices | |
| KR960011472B1 (en) | Manufacturing method of semiconductor memroy device | |
| KR100261991B1 (en) | Manufacturing method for transistor of semiconductor memory cell and its structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050721 Year of fee payment: 13 |
|
| LAPS | Lapse due to unpaid annual fee |