KR930007525B1 - Capacitor for semiconductor device and method for manufacturing thereof - Google Patents

Abstract

The semiconduct device capacitor useful as VLSI grode DRAM cell is mfd. by (a) forming a field oxide film (3), a gate (5) a source/ drain region (4) on the fixed region of a semiconductor substrate (1), (b) laminating a first oxide film (7), a first nitride film (8) and a second oxide film (9) on the whole surface, (c) selectively etching the layers (7,8,9) to expose the fixed part of the region (4), (d) etching the substrate of the region (4) to form a trench, (e) forming a first dielectric film (10) on the inner wall of the trench, (f) forming a second nitride film side wall (8a) on the side wall of the trench, (g) burying the inner part with a first polysilicon (11), (h) etching-back the polysilicon (11), and removing off the dielectric film (10), (i) forming a second dielectric film (10a) on the surface of the polysilicon (11), (j) forming a second polysilicon (12) on the whole surface, and patterning it, and (k) removing off the oxide film (9) and the nitride film (8), forming a third dielectric film (14) on the whole surface of the polysilicon (12), and forming a plate electrode on the film (14).

Description

Semiconductor device capacitors and manufacturing method thereof

1 is a side view of a typical VLSI stack capacitor cell.

2 is an equivalent circuit diagram of FIG.

3 is a cross-sectional view of a typical VLSI trench capacitor cell.

4 is an equivalent circuit diagram of FIG.

5 is a cross-sectional view of a DRAM cell of a parallel capacitor according to the present invention.

6 is an equivalent circuit diagram of FIG.

7 to 13 are manufacturing process diagrams of a DRAM cell of a parallel capacitor according to the present invention.

* Explanation of symbols for the main parts of the drawings

1 substrate 2 epitaxial layer

3: field oxide film 4: source and drain regions

5: gate 6: side wall

7: first oxide film 8: first nitride film

8a: second nitride film 9: second oxide film

10: first dielectric film 10a: second dielectric film

11: first polysilicon 12: second polysilicon

12a: Stacked storage node 13: photoresist

14 third dielectric film 15 plate electrode

16: bit line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) cell, and more particularly, to a DRAM cell of a parallel capacitor in which a capacitor is maximized by a parallel capacitor to be suitable for ULSI (Ultra Large Scale Intergrated Circuit) products of 16 megabytes or more.

Conventionally, stack capacitor cells and trench capacitor cells as shown in FIGS. 1 and 3 have been widely used.

However, according to the trend of higher integration, the number of devices mounted per unit area is increased, and the area used as a capacitor is reduced, which causes problems in obtaining capacitance required for operation of a DRAM cell.

That is, the stacked capacitor cell shown in FIG. 1 is a structure in which convex and convex portions are formed in order to increase the capacitor area and are sequentially stacked to form capacitors. VLSI (Very Large Scale Integrated Circuit) class, that is, 4 mega and 16 Effective capacitance can be obtained in the mega class, but the limit has been reached in the ultra-high density memory devices of the ULSI class of more than 16 mega class.

In addition, although the trench capacitor cell shown in FIG. 3 has a structure in which a trench is formed to increase the capacitor area, it is also difficult to secure a capacitance suitable for a ULSI class ultra-high density memory device.

2 and 4 are equivalent circuit diagrams of FIGS. 1 and 3, respectively.

The two structures as described above may be referred to as the most representative VLSI-class DRAM cell structure, but such a structure is difficult to obtain effective capacitance as a ULSI-class DRAM cell structure having a smaller design rule. It has a difficult problem.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a stack capacitor and a trench capacitor on one chip to provide a DRAM cell of a parallel capacitor suitable for ULSI products.

Another object of the present invention is to provide a DRAM cell manufacturing method of the parallel capacitor of the present invention. In order to achieve the above object, a feature of the present invention is to manufacture a semiconductor chip, which includes (a) forming a trench in the lower portion of the substrate using a first oxide film, a second nitride film, and a second oxide film as a mask, Forming a protruding first polysilicon to form a trench capacitor in which a spatula that is a trench capacitor is expanded; and (b) forming a stack storage node on the substrate, so that the entire surface of the stack storage node is a stack capacitor. There is a method of manufacturing a DRAM cell of a parallel capacitor consisting of a process of forming a stack capacitor to be used as an area.

According to another aspect of the present invention, in one semiconductor chip, a trench capacitor under a substrate in which polysilicon is protruded to increase a capacitor area inside a trench, and a stack capacitor on a substrate in which the entire surface of the capacitor storage node is used as the capacitor area. In the DRAM cell of the parallel capacitor.

Hereinafter, the present invention will be described in detail by the accompanying drawings.

5 is a cross-sectional view of a DRAM cell of a parallel capacitor according to the present invention, in which a stack capacitor and a trench capacitor are formed in parallel on one chip. The trench capacitor has a structure in which the capacitor area is increased by protruding the first polysilicon 11 from the inside of the trench, and the stack capacitor has a structure utilizing the entire surface of the storage node 12a as the capacitor area.

FIG. 6 is an equivalent circuit diagram of FIG. 5, in which the trench capacitor C _T and the stack capacitor Cs are connected in parallel to increase the capacitance of the memory cell.

Next, a DRAM cell manufacturing method of a parallel capacitor of the present invention will be described. 7 to 13 are manufacturing process diagrams of a DRAM cell of the parallel capacitor of the present invention. As shown in FIG. 7, the P ⁻ type epitaxial layer 2 is grown on the P ⁺ type substrate 1 (see FIG. 5), and the field oxide film 3 and the N ₁ type impurities Source and drain regions 4, gate 5 serving as word lines, sidewalls 6 are formed, and first oxide film 7, second nitride film 8, and second oxide film 9 are sequentially formed thereon. Afterwards, the first oxide film 7, the first nitride film 8, and the second oxide film 9 of the restricted portion on the source or drain region 4 are partially etched to form a trench.

Thereafter, as shown in FIG. 8, a trench is formed up to the p ⁺ type substrate 1, the first capacitor dielectric film 10 is formed inside the trench, and the second nitride film 8a is formed on the entire surface of the source or drain 4. After etching back to the lower surface to form the second nitride film sidewall 8a having a predetermined height on the inner side of the trench, the first polysilicon 11 is deposited on the entire surface to fill the trench. Thereafter, as shown in FIG. 10, the first capacitor dielectric layer 10 exposed to the inside of the trench, leaving only the first polysilicon 11 having the same height as the second nitride film sidewall 8a by etching back the first polysilicon 11. After stripping, the second nitride film sidewall 8a left inside the trench is stripped to leave only the first polysilicon 11 protruding from the trench and the second capacitor dielectric film on the polysilicon 11. It forms (10a).

The first polysilicon 12 is deposited on the entire surface including the inside of the trench to fill the trench, and then the first polysilicon 12 is patterned using a predetermined photoresist mask 13 to stack the storage node 12a. After forming, the first nitride film 8 and the second oxide film 9 on the first oxide film 7 are stripped, and a third capacitor dielectric film 14 is formed on the exposed surface of the stack storage node 2a. (Figures 11 and 12)

Thereafter, as shown in FIG. 13, the plate electrode 15 is formed on the third dielectric film 14, and the bit line 16 is formed in the predetermined region, thereby completing a parallel capacitance cell having sufficient capacitance.

As described above, the present invention efficiently utilizes the stack structure and the trench structure and connects them in parallel to increase the capacitance sufficiently, thereby sufficiently securing the capacitance necessary for the operation of the ULSI-class device structure, which has a smaller design rule than the VLSI class. There is an effect that can be.

Claims (5)

A process of forming the field oxide film 3, the gate 5, the source and the drain 4 in the predetermined region of the semiconductor substrate 1, the first oxide film 7, the first nitride film 8, and the second nitride film After stacking the myth films 9 sequentially, the second oxide film 9, the first nitride film 8, and the first oxide film 7 are exposed so that a predetermined portion of one region of the source or drain region 4 is exposed. Forming a trench by etching the semiconductor substrate in the exposed source or drain region (4), forming a first dielectric layer (10) on the inner wall of the trench, and forming a trench on the trench sidewall surface Forming a second nitride film sidewall (8a) having a height of < RTI ID = 0.0 >, < / RTI > filling the inside of the trench with first polysilicon (11), and making the first polysilicon (11) the same as the second nitride film (8a). Etching back to a height to thereby remove the first dielectric film exposed to the inside of the trench, Removing the sidewalls of the second nitride film, forming the second dielectric film 10a on the surface of the first polysilicon 11, and forming the second polysilicon 12 on the entire surface including the inside of the trench. Then patterning it into a capacitor storage node pattern 12a, removing the second oxide film and the first nitride film, forming a third dielectric film 14 on the entire surface of the second polysilicon, and the third And forming a plate electrode (15) on the dielectric film (14). The method of claim 1, wherein the second nitride film sidewalls are formed at a height corresponding to a bottom surface of the source or drain (4) at the bottom surface of the trench. The method of manufacturing a semiconductor device capacitor according to claim 1, further comprising a fixing for growing an epitaxial layer (2) on the semiconductor substrate (1). A gate 5 formed in a predetermined region of the semiconductor substrate 1, a source and drain region 4, a trench formed in one region of the source or drain region 4, and a first polysilicon 11 protruding from the center of the trench. ), The first dielectric film 10 formed on the inner wall of the trench, the second dielectric film 10a formed on the surface of the first polysilicon 11, and the second polysilicon formed on the top of the gate 5 while the trench is buried. 12a), a third dielectric film (14) formed on a surface of the storage node (12a), and a plate electrode (15) formed on the third dielectric film (14). The capacitance of the capacitor of claim 4, wherein the capacitance of the capacitor comprises the first polysilicon 11, the first and second dielectric layers 10 and 10a, and the storage node 12a, and the storage node 12a. And a capacitance of the stack capacitor including the third dielectric film 14 and the plate electrode 15.