KR930007326B1 - Variable bit field sign/non-sign abstracting processing circuit - Google Patents

Abstract

The circuit comprises the first barrel shifter (1) which obtains original signal data and outputs shifted data according to the offset signal, the 2nd barrel shifter (2) which obtains the above shifted data and outputs SIGN data shifted by the inverting signal of a bit width designating signal, the decoder (4) to decode the above signal.

Description

Variable bit field coded and unsigned extraction processing circuit

1 is a circuit diagram of the present invention.

2 is a logic table of a decoder of the present invention.

3 is a logical table of the barrel shifter of the present invention.

* Explanation of symbols for main parts of the drawings

1,2: barrel shifter 4: decoder

3: 4 input 1 output multiplexer

The present invention relates to a variable bit field code and unsigned extraction processing circuit in a 32-bit microprocessor, and more particularly, to a variable bit field code and unsigned extraction processing circuit for extracting a specifically designated bit field. .

In general, it is well known that computer graphics processing is mainly performed by data logic and arithmetic-sublimation grinding for each pixel. Each pixel data is composed of bit block data for efficient use of memory.

If the microprocessor processes the data of these bit blocks directly in hardware, the performance of the graphics processing program can be improved.

Conventionally, if only the data of any bit block of data output from a register in a 32-bit microprocessor is moved by a certain width, it cannot be configured by hardware. Therefore, it has to be processed by a program. There was an inconvenience that the complicated signal processing step must be performed.

Accordingly, an object of the present invention is to provide a variable bitfield coded and unsigned extraction processing circuit for extracting pixel data and transforming the pixel data into a general data format of a computer system. To this end, in the first barrel shifter in which original data is inputted from a register, the shifting data shifted by a bit size determined by an offset signal is output to a second barrel shifter and a four input one output multiplexer, and a second barrel is shifted. The shifter extracts the code data from the inverted 5-bit bit width designation signal and outputs the code data to the 4-input 1 output multiplexer so that the sign and unsignal signals through the inverter and the NOR gate and the bit width designation signal through the decoder The input or output multiplexer obtains the output of sign extraction or unsigned extraction.

Referring to the present invention in detail based on the accompanying drawings as follows. The first barrel shifter (S1), (S8), (S4), (S2), and (S1) to which the original data is input from the register in the processor to the input terminal (R) and are supplied to the selection terminals (S16), (S8), (S4), (S2) and (S1). In the output terminal ZN of 1), the input terminal R of the second barrel shifter 2 and the input terminals D2 and D3 of the four-input multiplexer 3 are simultaneously connected to each other. In the output terminal ZN of the second barrel shifter 2 which is connected to the selection terminals S16, S8, S4, S2, and S1 via the inverter I1, a four input one output multiplexer ( 3), and the unsigned signal (UNSIGN) is applied to the selection terminal (A) through the NOR gate (NR) like the sign signal (SIGN) after passing through the inverter (I2). The four-input one-output multiplexer 3, which is a 32-bit signal having a bit value of 1 by the decoder 4, is applied to the selection terminal B by the decoder 4, and the input terminal D1 has a value of zero. To ground (GND) It will be one output data is output from the output terminal (Z).

The signed and unsigned extraction circuit of the present invention configured as described above is configured to output 32-bit original data inputted from a register in a microprocessor and then output a shifted data output or a signed or unsigned data output. For example, if you want to unsign or sign 8 bits from bit 27 to bit 20 of the 32-bit value of the original data 1111, 1111, 1010, 1111, 1111, 1010, 1010, the 5-bit bit width designation signal is 8 The offset signal is inputted as a data value of 10011 minus 1 from a data value of 10100 corresponding to 20.

Therefore, the first barrel shifter applied to the offset signal 13H group selection terminals S16, S8, S4, S2, and S1 while the original data FFAAFFAAH is input to the input terminal R. In 1), as shown in the logic table of FIG. 3, the second barrel shifter 2 is output as the shifting data having data values of 1111, 1010, 1010, 1111, 1111, 1010, 1010, and 1111 from the output terminal ZN. Are simultaneously input to the input terminals R and D3 of the four-input one-output multiplexer 3. The second barrel shifter 2 receives the output of the first barrel shifter 1 as input terminals R31 to R0. A second barrel shifter applied to the selection terminals S16, S8, S4, S2, and S1 is inverted to 10111 while passing through the inverter I1. In the output terminal of 2), as shown in the logical table of FIG. 3, data values of 1010, 1111, 1111, 1010, 1010, 1111, 1111, and 1010 are outputted, and the data value of bit 25 is selected as a sign data value. Input 1 is input to the input terminal D0 of the multiplexer 3.

The bit width designation signal is decoded by the decoder 4 into values of 0000, 0000, 0000, 0000, 0000, 0000, 1111, and 1111 (see the logical table in FIG. 2) having a value of 1 by the corresponding bit size. When the decoded signal is applied to the selection terminal B of the 4-input 1-output multiplexer 3, and in the case of sign extraction, the input signal is set to 1 and the unsigned signal ONSIGN is set to 0. (I2) When 0 is input to the selection terminal A of the 4 input 1 output multiplexer 3 via the NOR gate NR and the bit width designation signal via the decoder 4 is 0, the input terminal D0 is turned off. In the case of 1, the output of the first barrel shifter 1 is selected by selecting the input terminal D3. That is, data output of 1111, 1111, 1111, 1111, 1111, 1111, 1111, 1010 is output.

In the case of unsigned extraction, the sign signal (SIGN) and the unsigned signal (UNSIGN) and 0 and 1 are respectively inputted, and 1 is input to the selection terminal A while only the input terminal D1 and the input terminal D3 are selected. The data output of 0000, 0000, 0000, 0000, 0000, 0000, 1111, 1010 is outputted.

Therefore, the variable bit field coded and unsigned extraction processing circuit of the present invention outputs the shifted data in which the original data input by the first barrel shifter 1 is shifted by the offset signal. The second barrel shifter (2) receiving the shift data is shifted by the bit width designation signal to extract the sign data and applied to the input terminal (D0) of the 4-input 1 output multiplexer (3). While receiving the shift data of the shifter 1 through the input terminals D2 and D3, a data output consisting of the shift data and the sign signal or the unsigned signal is generated according to the input of the bit width designation signal and the sign signal or the unsigned signal. To output it.

Claims (1)

A first barrel shifter (1) for receiving original data and outputting shift data shifted by a bit specified by an offset signal; and receiving the shift data provided from the first barrel shifter (1). A second barrel shifter 2 for shifting the bit width by a bit determined by the inversion signal of the bit width designation signal and outputting code data, a decoder 4 for decoding the bit width designation signal, and a decoder of the decoder 4 A four-input one-output multiplexer (3) which is controlled by an output signal and a sign signal (SIGN) or an unsigned signal (UNSIGN) to selectively output either the shifting data of the original data or zero or the sign data. And a mask bit field code and unsigned extraction processing circuit.