KR100770448B1 - Bit extracting device and microprocessor using this bit extracting device - Google Patents

Abstract

The present invention relates to a bit extractor for efficiently extracting consecutive bits necessary in a process of restoring variable length coded data to enable real-time processing. The bit extractor according to the present invention includes a memory data storage unit, a residual data alignment unit, a bit extractor, and a controller. The memory data storage unit reads and stores data from the memory. The residual data alignment unit performs byte alignment on the remaining data extracted from the data received from the memory data storage unit. The bit extractor extracts the bit data from the residual data alignment unit and right-aligns the bit data. The control unit reads a shift control signal for causing the bit extracting unit to output a predetermined number of bits and a memory reading for causing the memory data storage unit to read the next data in the memory when all data stored in the memory data storage unit are extracted through the bit extracting unit. Generate an enable signal.

Bit Extraction, Variable Length Coding, Barrel Shift Circuit, Memory Operation

Description

BIT EXTRACTING DEVICE AND MICROPROCESSOR USING THIS BIT EXTRACTING DEVICE}

1 is a block diagram of an entire system to which a bit extraction apparatus according to the present invention is applied.

2 is a block diagram of a bit extracting unit according to an embodiment of the present invention;

3 is a block diagram of a control unit according to the present invention.

4 is a block diagram of a bit extracting unit according to another embodiment of the present invention;

[Description of Reference Symbol in Drawing]

101: memory 103: bit extraction unit

105: control unit S1 S3: barrel shift circuit

R1, R5: Registers M1, M3: Multiplexers

301: Number of extracted bits register 303: Address counter

305: shift bit counter 307: control signal generation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit extractor, and more particularly, to a bit extractor capable of efficiently extracting consecutive bits required in a process of restoring variable length coding (VLC) data in real time. .

With the development of the Internet and information processing technology, the need for transmitting large amounts of data is increasing day by day. Various compression and decompression techniques are used to efficiently transmit large amounts of data on limited communication channels, and the core of these techniques is to use variable length codes such as Huffman codes.

Historically, dedicated processors for various purposes have emerged as needed. However, the problem of hardware processing of data compression and decompression has only recently become important, and so far, most of them have been implemented by installing software in general-purpose processors such as digital signal processors (DSPs).

In order to process the variable length code in hardware, it is necessary to continuously extract necessary bits from data stored in memory in byte or word units. At this time, the extracted bits must be right aligned to suit the processing of the next process, and the remaining bits must be left aligned for the next extraction. The difficulty here is that because the number of bits used does not have a certain length, it is necessary to ignore the boundaries of the data stored in memory and break the bits as necessary.

Barrel shifters and arithmetic / logix units (hereinafter referred to as ALUs) are essential for the performance of these processes. In general DSPs, barrel shifters may not be provided. Even if provided, processing such complex operations with only the ALU and barrel shift circuits is quite inefficient, ie, the amount of computation increases and a very large number of memory reads are required.

Accordingly, an object of the present invention is to propose a more efficient hardware structure for extracting as many bits as necessary continuously.

Another object of the present invention is to propose a microprocessor which efficiently performs bit extraction operations.

In order to achieve the above object, the present invention is a device for continuously extracting bit data from the data stored in the memory, and includes a memory data storage unit, a residual data alignment unit, a bit extracting unit and a control unit. The memory data storage unit reads and stores data from the memory. The residual data alignment unit performs byte alignment on the remaining data extracted from the data received from the memory data storage unit. The bit extractor extracts the bit data from the residual data alignment unit and right-aligns the bit data. The control unit reads a shift control signal for causing the bit extracting unit to output a predetermined number of bits and a memory reading for causing the memory data storage unit to read the next data in the memory when all data stored in the memory data storage unit are extracted through the bit extracting unit. Generate an enable signal.

The memory data storage unit includes a first register, a first barrel shift circuit, and a first multiplexer. The first register stores L bits of word data read from the memory. The first barrel shift circuit receives word data stored in the first register, shifts the input data by the bit specified by the shift control signal, and outputs the shifted result. When the first multiplexer reads data from the memory, the first multiplexer receives the read data and outputs the read data to the first register. After the first barrel shift circuit performs the shift operation, the first multiplexer receives the L bit, which is the result of the shift, is output to the first register. do.

The remaining data alignment section includes a second register and a second barrel shift circuit. The second register stores M bits of data. The second barrel shift circuit receives the L bit data stored in the first register as the lower bit data, receives the M bit data stored in the second register as the upper bit data, and receives the bit specified by the shift control signal. After shifting the data, the shifted M bit is fed back to the second register. The residual data alignment unit preferably further includes a second multiplexer which receives the output data read out from the memory and the M bit data which is the output from the second barrel shift circuit and outputs any data to the second register.

The bit extracting section includes a third register, a third barrel shift circuit, and a third multiplexer. The third register stores N bits of data. The third barrel shift circuit receives the M bit data stored in the second register as the low bit data, the N bit data stored in the third register as the high bit data, and inputs the bit specified by the shift control signal. After shifting the received data, output the shifted result. The third multiplexer receives the N bits, which are output data of the shifted result after the third barrel shift circuit performs the shift operation, and outputs the N bits to the third register, and after the data stored in the third register is read, 0 bits of N bits. The data is input and output to the third register.

The control unit further generates an address signal indicating the location of the memory from which data is read in accordance with the memory read enable signal. In addition, the control unit reads a new data word from the memory and stores it in the first register, and then determines the number of bits shifted in the first barrel shift circuit and the number of bits to be shifted from the contents of the data stored in the second register. Create After the new data word is read from the memory and stored in the first register, the controller generates a memory read enable signal when the number of bits shifted in the first barrel shift circuit is equal to the number of bits of the data word. The control unit also generates a load enable signal for enabling loading of the first to third registers after the shift in the first to third barrel shift circuits.

The control unit includes: an extraction bit number register for storing the number of bits to be extracted; an address counter for generating an address of a data word to be read according to the memory read enable signal; and a new data word is read from the memory and stored in the first register. And compares the bit number counter for storing the shifted bit number in the first barrel shift circuit with the shifted bit number from the bit number counter and the number of bits to be extracted from the extraction bit number register. And a control signal generator for generating an enable signal.

The number of bits L of data stored in the first register is preferably the number of word bits of the memory. It is also preferable that the number of bits of the second register is equal to the number of bits of the memory word, and the number of output bits of the second barrel shift circuit is also equal to the number of bits of the memory word.

It is preferable to further include the fifth to sixth registers for backup which temporarily store the bit streams which have been previously processed to process several separate bit streams. The fifth register receives data stored in the second register as an input and provides it as an input of the second multiplexer, and the sixth register receives data stored in the first register as an input and provides it as an input of the first multiplexer. In addition, it is preferable to further include a data bus connected to the output terminal of the first to third registers for data transmission with other components, and to one input terminal of the first to third multiplexers.

Through the above-described configuration, the necessary bits are sequentially extracted as water flows, thereby performing memory operations only when reading new data, thereby eliminating unnecessary memory operations.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; Like reference numerals in the drawings indicate the same or similar components.

1 is a block diagram of an entire system to which a bit extraction apparatus according to the present invention is applied. In FIG. 1, 101 denotes a memory, 103 denotes a bit extractor, and 105 denotes a controller. The bit extracting unit 103 reads data from the memory 101 in units of words through the memory output terminal RamOut and stores the data. The control unit 105 reads the byte-aligned residual data from the bit extraction unit 103 through the output terminal Out1. The control unit 105 generates a shift control signal ShiftAmt that specifies how many bits to extract from the remaining data to the bit extraction unit 103, and the bit extraction unit 103 transmits the stored data. By shifting, as many bits as the number of bits specified by this shift control signal ShiftAmt are extracted and output through the output terminal Out2. The control unit 105 generates a load enable signal LoadEn and transmits the load enable signal LoadEn to the bit extracting unit 103 so as to store the state of the extracted data. The bit extracting unit 103 transmits the load enable signal therein. It is used as a load enable signal of the provided registers. When all data newly read from the memory 101 and stored in the bit extracting unit 103 are extracted from the bit extracting unit 103, the control unit 105 generates a memory read enable signal RamRead. New data is read out and stored in the bit extraction section 103 via the memory output terminal RamOut. The controller 105 determines the generation time of the memory read enable signal RamRead by monitoring the shift control signal ShiftAmt generated after the new data is stored in the bit extraction unit 103 from the memory 101. The position of the memory 101 to which data is to be read is specified by the memory address signal RamAddr generated by the control section 105.

2 is a block diagram of a bit extracting unit according to an embodiment of the present invention. As shown in FIG. 2, the bit extracting unit according to the present embodiment serially integrates three barrel shifting circuits S1, S2, and S3 having a barrel shifting function to continuously perform a continuous bit extraction process. It is a structure arranged. The bit extracting unit according to the present embodiment further includes three registers R1, R2, and R3, and three multiplexers M1, M2, and M3.

The barrel shift circuits S1, S2, S3 are all left shift circuits or right shift circuits. However, in the case of the light shift circuit, the roles of R1 and R3 are reversed, and thus the connection relationship is also changed. The output of each register is connected to the input of the corresponding barrel shift circuit, and the output of the second register R2 is transferred to the output terminal OUT1 and the output of the third register R3 is transferred to the output terminal OUT2. The number of bits in the register and shift circuit matches the number of output bits in the memory. However, the number of bits of R2 and R3, S3 and S2, M3 and M2 is one byte (8 bits), and only the number of bits of R1, M1, and S1 can be equal to the number of bits in the memory word. Alternatively, the number of bits in each register may be configured as an integer multiple of the number of bits in the memory word. Such slight variations can be modified as many as the intention of the skilled designer.

The first register R1, the first barrel shift circuit S1, and the first multiplexer M1 constitute a memory data storage unit for reading and storing data from the memory 101. The first multiplexer M1 receives the memory output via the memory output terminal RamOut and the output of the first barrel shift circuit S1 as two inputs, and outputs them to the first register R1 according to the bit extraction process. do. Data read from the memory 101 and stored in the first register R1 is stored in the upper bits of the first barrel shift circuit S1, and the lower bits contain zero data having the same number of bits as the number of bits of the memory word. Stored. After the data is stored in the first barrel shift circuit S1 in this manner, the result shifted to the left by a predetermined number of bits, for example, is stored in the first register R1 via the first multiplexer M1. How much is shifted in the 1st barrel shift circuit S1 is specified by the shift control signal ShiftAmt produced | generated by the control part 105 as mentioned above. Storing the same number of zero data as the number of bits of the memory word in the lower bits of the first barrel shift circuit S1 is such that the first barrel shift circuit S1 has the same size as the other barrel shift circuits S2 and S3. To do that.

The second register R2, the second barrel shift circuit S2, and the second multiplexer M2 form a residual data alignment unit for byte-aligning the extracted data remaining from the data received from the memory data storage unit. The residual data alignment provides byte aligned data (reference output) to determine the bits to be actually extracted. The second multiplexer M2 has, as its input, upper bit data of a memory word size among the data read from the memory 101 and the data stored in the second barrel shift circuit S2, and these two inputs are used to extract data. Therefore, it is output to the second register R2. First, data read from the memory 101 is stored in the second register R2 via the second multiplexer M2. The contents stored in the second register R2 are stored in the upper bits of the second barrel shift circuit S2, and the contents stored in the first register R1 are stored in the lower bits. The content stored in the second barrel shift circuit S2 shifts the data to the left, for example, by the number of bits specified by the shift control signal ShiftAmt in the same way as the first barrel shift circuit S1. The resulting data of the memory word size is fed back to the input of the second multiplexer M2.

The number of bits of the second register R2 must be greater than or equal to the number of bits referred to by the VLC decoding circuit of FIG. 3. However, it is preferable that the number of bits of the second register R2 is the same as the number of bits of the memory word, and the number of bits of the output of the second barrel shift circuit S2 is also the same as the number of bits of the memory word. The content stored in the second register R2 is output through the first output terminal OUT1 and is provided to, for example, an input of a VLC decoding circuit. Determine how many bits of the code to be extracted next from the VLC decoding circuit are. This determination may be performed while the second register R2 is filled with data. Therefore, the first register R1 as well as the second register R2 must be filled with data read into the memory 101 during the initialization process. The second multiplexer M2 is provided to quickly perform this initialization process. If there is no second multiplexer M2, data must be stored in the first register R1 first, then shifted in the second barrel shift circuit S2 and stored in the second register R2. .

In addition, the third register R3, the third barrel shift circuit S3, and the third multiplexer M3 form a bit extraction unit that extracts the right bit data from the remaining data alignment unit and right-aligns the same. The third multiplexer M3 receives data having all bits 0 and the output of the third barrel shift circuit S3 as an input, and outputs one of the data to the third register R3. In the third barrel shift circuit S3, data stored in the third register R3 is input to the upper bits thereof, and data stored in the second register R2 is input to the lower bits thereof.

After extracting the necessary data from the third register R3 through the second output terminal OUT2 and before extracting the next data, the zero data is passed through the third multiplexer M3 with all the bits of the third register R3. The upper bit of the third barrel shift circuit S3 is loaded. That is, the upper bits of the third register R3 and the third barrel shift circuit S3 are cleared. Through this, by implementing the function of the barrel shift circuit, the data stored in the third register R3 is actually used in the next processing. However, when implementing a VLC decoder such as the Huffman decoder, the shifted and stored values in the third register R3 are not directly used but discarded. In this case, the third register R3 is not necessary. That is, when a decoder table is read using the value of the second register R2 output through the first output terminal OUT1, when a match is found, the output value from the table is actual information desired. The number of bits of data actually used in the matching process among the data stored in the second register R2 becomes the number of bits GetAmt to be shifted next. In this case, it is not necessary to clear the third register R3 every time.

3 is a block diagram of a control unit according to the present invention. In FIG. 3, 301 is an extraction bit number register, 302 is a VLC decoding circuit, 303 is an address counter 303, 305 is a shift bit counter, and 307 is a shift control signal ShiftAmt or a memory read enable signal RamRead. Respectively indicate the control signal generator.                     

The extraction bit number register 301 is a register that stores the number of bits to be extracted. As described above with reference to FIG. 2, the number of bits to be extracted, that is, the number of bits to be shifted, outputs the data aligned by the byte or left-aligned to the second register R2 through the first output terminal OUT1 to output the VLC. The determination is made by inputting to the decoding circuit 302. As shown in Fig. 3, the extraction bit number register 301 constitutes a control signal generator 307 and a feedback circuit. When the number of bits GetAmt to be extracted is greater than the number of bits of data remaining in the first register R1, first, the number of bits of data remaining in the first register R1 is shifted by the number of bits remaining, and the data of the remaining number of bits is The data is newly read from the memory 101, stored in the first register R1, and then shifted. In this process, it is necessary to adjust the number of bits (GetAmt) to be extracted twice. For this purpose, a feedback circuit is configured. The VLC decoding circuit 302 may be included in the controller 300 or may be configured separately.

The address counter 303 generates an address RamAddr of a data word to be read according to the memory read enable signal, and the shift bit number counter 305 reads a new data word from the memory and stores it in the first register R1. After that, the number of bits shifted in the first barrel shift circuit S1 is counted. The address counter 303 and the shift bit number counter 305 are composed of one register. When the memory word is 8 (= 2 ³ ) bits, the lower 3 bits correspond to the shift bit number counter 305. In FIG. 3, the address counter 303 and the shift bit number counter 305 are strictly registers, and function as a counter by being defective with the adder 304. However, here, for the sake of convenience, only the counter is referred to. The total counter value is combined by the shift control signal ShiftAmt and the adder 304 to generate the next counter value. Since one word of data from the memory 101 is stored in the first register R1, if there is an 8-bit shift after new data is stored in the first register R1, a new data word must be read from the memory 101. . Shifts within 8 bits are counted in the shift bit counter 305, and shifts of 8 bits or more are counted in the address counter 303 to generate an address RamAddr of a new data word.

The control signal generation unit 307 compares the shifted bit number BitCnt from the shift bit number counter 305 with the bit number GetAmt to be extracted from the extraction bit number register 301 and shifts the shift control signal ShiftAmt. Or a memory read enable signal RamRead. As described above, the shift control signal ShiftAmt specifies the number of bits shifted in the first to third barrel shift circuits S1, S2, and S3. When the number of bits GetAmt to be extracted is larger than the number of bits remaining in the first register R1, that is, 8 BitCnt, the shift control signal ShiftAmt that first specifies the number of bits remaining in the first register R1. ) Is generated. Next, after a new data word is read from the memory 101 and stored in the first register R1, a shift control signal ShiftAmt is specified which specifies the remaining number of bits. The memory read enable signal RamRead is generated when a new data word is to be read from the memory 101. Loading in which enables loading of registers R1, R2, R3 to store the shifted state after the shift operation is performed in the first to third barrel shift circuits S1, S2, S3. The enable signal LoadEn is also generated in the control signal generator 307.

The sequential logic portion of the control unit 300 may be provided in the form of micro-programmed control or hardwiring control in the central control unit of the processor.

Hereinafter, a process of continuously extracting Huffman coded bits of various lengths in an embodiment of the present invention will be described with reference to FIGS. 2 and 3. It is assumed that the number of bits of the data word of the memory is 8 bits, and the data to be extracted is sequentially stored from address 0 of the memory.

First, the first data of the memory is read into the first register R1 as an initialization condition (R1 <-MEM [0]). At this time, the total counters 303: 305 indicate 8, which is the next address. The memory address does not use the lower three bits of this counter, so the actual address is one. When the bit extractor of the present invention is used for Huffman coding, it is necessary to read the byte aligned data to know how many bits to extract. The first output terminal OUT1 is used for this purpose. Therefore, all bits of the second register R2 must always be full. Therefore, the second register R2 is filled into 8 by inserting 8 into the register 301 that stores the number of bits to be extracted. There are two ways to fill the second register R2. One is to transfer the MEM (0) stored in the first register R1 to the second register R2 via the second barrel shift circuit S2. The MEM (1) is stored in the first register R1, and the other is the MEM (0) stored in the second register R2 directly from the memory 101 using the second multiplexer M2. After that, the MEM (1) is stored in the first register R1. The latter method is more preferred when considering the processing speed. Up to this state is the initialization process, and the total counters 303 and 305 represent 16 and the address counter 303 represents 2.

If the required number of bits GetAmt is now 4, 4 is stored in the extraction bit number register 301, which is compared with the number of bits remaining in the first register R1. Currently, both the second register R2 and the first register R1 are full, and the third register R3 is initialized to zero. The number of bits (bit_rest) remaining in the first register is (8-BitCnt), so 8-0 = 8. Since the remaining number of bits (bit_rest) is larger than the required number of bits (GetAmt), all four bits are extracted at once. That is, since the shift control signal ShiftAmt becomes 4, the first to third registers R1, R2, and R3 are shifted left by 4 bits. After this process, the memory address RamAddr is 2 and the extracted bit BitCnt is 4.

In this state, it is assumed that the next required number of bits is five. This time, since the remaining number of bits (bit_rest) is 8-4 = 4 and the required number of bits (GetAmt) is 5, the shift control signal ShiftAmt selects 4, the maximum number of bits remaining. After the shift, the first register R1 is completely empty, the required number of bits GetAmt is 5-4 = 1, the value of the address counter 303 AddrCnt is 3, and the extracted bits are The number BitCnt is zero. Now, the value of the third word MEM [2] of the memory is filled in the first register R1, the remaining one bit is shifted, and the result is output to the second output terminal OUT2. In the rest of the process, one of the two previous examples is repeated.                     

4 is a block diagram of a bit extracting unit according to another embodiment of the present invention. In FIG. 4, R4 is a backup register for the first register R1 and R5 is a backup register for the second register R2. The control unit for this bit extraction unit is almost the same as that shown in FIG. The bit extractor shown in FIG. 4 serves as one component of a processor, and is connected through a data bus (DataBus) for data transmission with other components such as an ALU or a memory. The number of bits of the register, multiplexer and barrel shift circuit is an integer multiple of the number of bits of the memory word or an integer multiple of the number of bits of the basic word of the processor. In FIG. 4, data exchange with another computing unit of another processor is performed by direct connection such as one or more data buses and a first output terminal OUT1. The multiplexer can be adjusted to have more or less selection inputs depending on various input relationships and bus structures. Unlike the configuration of the bit extractor shown in FIG. The backup registers R4 and R5 for temporarily storing the data are provided together. Backup registers R4 and R5 may be omitted, and more may be used (eg, R3 backup registers). A backup counter such as the backup register of FIG. 4 may be added to the controller. The structure of FIG. 4 may provide a right shift function only with a left shift circuit.

The above-described configuration can greatly reduce the number of accesses to the memory while implementing the bit extraction operation in hardware, thereby greatly improving the processing speed. In particular, in the case of designing a specialized microprocessor such as a bit arithmetic processor including a bit extraction operation using the configuration according to the present invention, the processing speed of the processor is significantly improved.

Claims (18)

An apparatus for continuously extracting bit data from data stored in a memory, A memory data storage unit for reading and storing data from the memory; A residual data alignment unit for byte-aligning data received from the memory data storage unit; A bit extraction unit for extracting a right number of bit data from the residual data alignment unit and right-aligning the extracted data; A shift control signal for causing the bit extracting unit to output the predetermined number of bit data; and when all data stored in the memory data storage unit are extracted through the bit extracting unit, the memory data storage unit causes the next data of the memory to be extracted. A control unit for generating a memory read enable signal Bit extraction apparatus comprising a. The method of claim 1, The memory data storage unit A first register for storing L bit word data read from the memory; A first barrel shift circuit for receiving word data stored in the first register, shifting data received by a bit specified by the shift control signal, and outputting a shifted result; When reading data from the memory, the read data is input to the first register, and after the first barrel shift circuit performs the shift operation, the L bit, which is the result of the shift, is received and output to the first register. The first multiplexer Bit extraction apparatus comprising a. The method of claim 2, The remaining data alignment unit A second register for storing data of M bits, Shift the data received by the bit specified by the shift control signal by receiving L bit data stored in the first register as low bit data, M bit data stored in the second register as high bit data And a second barrel shift circuit for feeding back the M bit, which is the result of the shift, to the second register. Bit extraction apparatus comprising a. The method of claim 3, The bit extraction unit A third register for storing N bits of data, Shifting the data received by the bit specified by the shift control signal by receiving the M bit data stored in the second register as the lower bit data, the N bit data stored in the third register as the upper bit data A third barrel shift circuit for outputting the shifted result after the After the third barrel shift circuit performs the shift operation, it receives an N bit that is the result of the shift and outputs the result to the third register. After reading the data stored in the third register, the N bit 0 data is received. A third multiplexer outputting to the third register Bit extraction apparatus comprising a. The method of claim 4, wherein And the controller is further configured to generate an address signal indicating a location of the memory from which data is read according to the memory read enable signal. The method of claim 4, wherein The controller generates the shift control signal by determining a number of bits to be shifted by the number of bits shifted in the first barrel shift circuit after a new data word is read from the memory and stored in the first register. Bit extraction device. The method of claim 6, The controller may be configured to generate the memory read enable signal when a new data word is read from the memory and stored in the first register, and the number of bits shifted in the first barrel shift circuit is the same as the number of bits of the data word. Bit extraction apparatus characterized in. The method of claim 4, wherein And the control unit generates the shift control signal by determining the number of bits to be shifted from contents of data stored in the second register. The method of claim 4, wherein And the control unit generates a load enable signal for enabling loading of the first to third registers after the shift in the first to third barrel shift circuits. The method of claim 4, wherein The control unit An extraction bit number register for storing the number of bits to be extracted; An address counter for generating an address of a data word to be read according to the memory read enable signal; A bit number counter for storing the number of bits shifted in the first barrel shift circuit after a new data word is read from the memory and stored in the first register; A control signal generator configured to generate the shift control signal or the memory read enable signal by comparing the shifted bit number from the bit counter with the number of bits to be extracted from the extraction bit number register Bit extraction apparatus comprising a. The method of claim 4, wherein And the number of bits L of data stored in the first register is the number of word bits of the memory. The method of claim 11, And the first barrel shift circuit stores 2 L bits of data, data stored in the first register is input as upper bits, and L zero data is input as lower bits. The method of claim 4, wherein And a second multiplexer which receives output data read from the memory and M bits of data output from the second barrel shift circuit as inputs and outputs any data to the second register. Device. The method of claim 13, And the number of bits M of data stored in the second register is equal to the number of word bits of the memory, and the number of output bits of the second barrel shifter is equal to the number of word bits of the memory. The method of claim 14, Further comprising a fifth register and a sixth register, The fifth register receives data stored in the second register as an input and provides the input to the input of the second multiplexer, And the sixth register receives data stored in the first register as an input and provides the input to the input of the first multiplexer. The method of claim 4, wherein And a data bus connected to the output terminals of the first to third registers and to one input terminal of the first to third multiplexers. An apparatus for continuously extracting bit data from data stored in a memory, First to third registers for storing data, wherein the first register stores L bits of data, the second register stores M bits of data, and the third register stores N bits of data The data stored in the third register is used as an output of the bit extraction apparatus; A first barrel shift circuit for receiving L-bit data stored in the first register, shifting the data input by the bit specified by the shift control signal, and outputting the shifted result; When reading data from the memory, the read data is input to the first register, and after the first barrel shift circuit performs the shift operation, the L bit, which is the result of the shift, is received and output to the first register. The first multiplexer, Shift the data received by the bit specified by the shift control signal by receiving L bit data stored in the first register as low bit data, M bit data stored in the second register as high bit data A second barrel shift circuit for feeding back the M bit, which is the result of the shifted result, to the second register; Shifting the data received by the bit specified by the shift control signal by receiving the M bit data stored in the second register as the lower bit data, the N bit data stored in the third register as the upper bit data A third barrel shift circuit for outputting the shifted result after the After the third barrel shift circuit performs the shift operation, it receives an N bit that is the result of the shift and outputs the result to the third register. After reading the data stored in the third register, the N bit 0 data is received. A third multiplexer outputting to the third register, Generating a shift control signal specifying a number of bits to be shifted by the first to third barrel shift circuits and a memory read enable signal instructing reading of data from the memory; Control Bit extraction apparatus comprising a. A microprocessor for performing a bit extraction operation, First to third registers for storing data, wherein the first register stores L bits of data, the second register stores M bits of data, and the third register stores N bits of data The data stored in the third register is used as an output of the bit extraction apparatus; A first barrel shift circuit for receiving L-bit data stored in the first register, shifting the data received by the bit specified by the shift control signal, and outputting the shifted result; When reading data from the memory, the read data is input to the first register, and after the first barrel shift circuit performs the shift operation, the L bit, which is the result of the shift, is received and output to the first register. The first multiplexer, Shift the data received by the bit specified by the shift control signal by receiving L bit data stored in the first register as low bit data, M bit data stored in the second register as high bit data A second barrel shift circuit for feeding back the M bit, which is the result of the shifted result, to the second register; Shifting the data received by the bit specified by the shift control signal by receiving the M bit data stored in the second register as the lower bit data, the N bit data stored in the third register as the upper bit data A third barrel shift circuit for outputting the shifted result after the After the third barrel shift circuit performs the shift operation, it receives an N bit that is the result of the shift and outputs the result to the third register. After reading the data stored in the third register, the N bit 0 data is received. A third multiplexer outputting to the third register, A shift control signal specifying a number of bits to be shifted by the first to third barrel shift circuits, and a memory read enable signal instructing data read from the memory; Microprocessor including a bit extraction device having a control unit.

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