KR19980023743A - Data Extraction & Fittings - Google Patents

Abstract

The present invention relates to a data extraction and fitting apparatus for converting data having various bit widths into multiple pieces of data in a video encoding / decoding system and converting the multiplexed data into pieces of individual data having appropriate sizes. It is about. This apparatus of the present invention includes a register 202 for storing multiplexed data of a predetermined size; A bit width information storage unit 123 for storing bit width information of individual data stored in the register in advance; A bit width information extractor 210 for sequentially outputting bit width information stored in the bit width information storage unit; An accumulator 220 which receives bit width information from the bit width information extractor and accumulates its output; A mask signal generator 230 receiving bit width information from the bit width information extractor and generating a mask signal; A barrel shifter (203) for outputting predetermined data by shifting the data stored in the register according to the output of the accumulator; And a mask unit 204 for extracting and fitting data by masking the output of the barrel shifter according to the mask signal, and extracting individual data from the multiplexed data and fitting the data to a predetermined size.

Description

An apparatus for extracting and fitting data from multiplexed data

The present invention relates to a data extraction and fitting apparatus for converting data having various bit widths into multiple pieces of data in a video encoding / decoding system and converting the multiplexed data into pieces of individual data having appropriate sizes. It is about.

In general, in the video encoding field, it is necessary to multiplex the transmitted data in a compact structure in order to reduce redundancy in transmitting data. For example, while the size of the data bus width for transmission is 16 bits, when the bit width of the data actually to be transmitted varies from 1 bit to 16 bits, a plurality of data are combined to form one 16-bit data. It may be efficient to send at once. That is, Table 1 below is an example of one multiplexed data format formed by combining data of various bit widths.

beat D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 DD5 D4 D3 D2 D1 D0 data F6 F5 F4 F3 F2 F1 Bit width One 4 One 5 2 3

The 16-bit data D0 to D15 multiplexed in Table 1 includes F1 data D0 to D2 having a beep width of 3 bits, F2 data D3 and D4 having a width of 2 bits, and a width of 5 bits. Combination of F3 data (D5 to D9), F4 data (D10) having a width of 1 bit, F5 data (D11 to D14) having a width of 4 bits, and F6 data (D15) having a width of 1 bit. consist of.

If the six individual data F1 to F6 are transmitted using the 16-bit data bus without multiplexing, at least six bus cycles are required, but the multiplexed 16-bit data can be transmitted in one bus cycle. . Therefore, when combining data having various small bit widths and transmitting them as multiplexed data having a constant size, transmission efficiency can be improved.

Meanwhile, as is well known, headers such as a sequence header, a picture header, etc. in an MPEG2 bit stream are defined as a combination of bits having various variable lengths, and the size is defined in the ISO / IEC standard. have. For example, a picture header has a 32-bit picture start code (picture_start_code) followed by a 10-bit temporal_reference, followed by a 3-bit picture coding type (picture_coding_type), and a 16-bit virtual buffer delay (vbv_delay). ) ..... and so on. As such, when variable length information is transmitted from an actual system (MPEG coder or decoder), the fixed length unit (for example, 32 bits or 16 bits, etc.) will be bundled and transmitted. It will consist of a combination of data having a bit width.

However, when the multiplexed data is processed in the system, it is separated into individual data and fit and processed to a certain length. For example, as shown in Table 1, the data D0 to D15 multiplexed with six individual data are divided into data of a predetermined length (for example, 8 bits or 16 bits) in the system and processed.

Accordingly, in an image encoding or decoding system that processes multiplexed data having various bit widths in terms of transmission efficiency or standard, an apparatus for extracting and fitting the multiplexed data into individual data having a predetermined length is required.

Accordingly, an object of the present invention is to provide an apparatus for extracting and fitting individual data having various bit widths from multiplexed data in an image encoding or decoding system in order to satisfy the above needs.

In order to achieve the above object, the apparatus of the present invention receives data obtained by multiplexing at least one or more individual data, and from the bit width information storage unit in which information on the bit width of the individual data is stored in advance. A data extraction and fitting device for fitting a predetermined length after extracting the individual data, comprising: a register for latching and storing multiplexed data having a predetermined size; Bit width information extraction means for sequentially outputting bit width information stored in the bit width information storage unit; An accumulator which receives bit width information from the bit width information extracting means and accumulates the output thereof; Mask signal generating means for receiving bit width information from said bit width information extracting means and generating a mask signal; A barrel shifter configured to output data having a predetermined size by shifting data stored in the register according to the output of the accumulator; And masking means for fitting data by masking the output of the barrel shifter according to the mask signal.

As described above, the data extracting and fitting unit moves the data to be extracted by the barrel shifter to the lower bit or upper bit area, extracts the desired individual data according to the bit width information from the mask unit, and the remaining bits are 0. By filling in, the individual data can be easily extracted from the multiplexed data.

1 shows an example of a part of a general imaging system to which the present invention is applied;

2 is a block diagram showing a data extraction and fitting apparatus according to the present invention;

3 is a detailed block diagram of a mask signal generator shown in FIG. 2;

4 is a detailed block diagram of a mask unit shown in FIG. 2;

5 is a view for explaining an example of the operation according to the present invention;

6 is an example of a data format formed according to a data extraction operation result in the example shown in FIG. 5;

7 is a timing diagram illustrating an example of operation according to the present invention.

* Explanation of symbols for main parts of the drawings

100: host controller 120: image encoder

121: bus matching unit 122: data extraction and fitting unit

123: Bit width information storage unit (ROM) 124: RAM

125: RAM controller 201, 205: buffer

202: register 203: barrel shifter

204: mask unit 210: bit width information extractor

220: accumulator 230: mask signal generator

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an example of a general video encoding system to which the present invention is applied, FIG. 2 is a block diagram illustrating a data extraction and fitting apparatus according to the present invention, and FIG. 3 is a detailed block diagram of a mask signal generator shown in FIG. 2. 4 is a detailed block diagram of the mask unit illustrated in FIG. 2.

The video encoding system to which the present invention is applied is composed of an encoder 120 which receives 16 bits of data from the host controller 100 through a data bus and encodes the encoded data. The encoder 120 includes a bus matching unit 121 and data extraction. The unit 122 includes a bit width information storage unit 123, a RAM 124, and a RAM controller 125.

In FIG. 1, the bus matching unit 121 matches the host bus with various addresses and data output from the host controller 100 to the encoder 120, and the bit width information storage unit 123 is a ROM. Implemented in the same memory, and stores the information about the bit width of each individual data contained in the data input through the data bus in advance.

In addition, the data extracting unit and the fitting unit 122 of the present invention latch the data input from the bus matching unit 121 and then receive the bit width information from the bit width information storage unit 123 to extract individual data, and then fit the same. The RAM 124 stores data output by the data extractor and the fitting unit 122 according to the address (add) and the control signal (r / w) of the RAM controller 125. do. At this time, when the extraction completion signal is input from the bus matching unit 121, the RAM controller 125 stops the data storage operation.

Therefore, the multiplexed data inputted through the data bus by the data extraction and fitting unit 122 according to the present invention is divided into individual data and then stored in the RAM 124, and the encoder 120 is stored in the RAM 124. The stored data is processed by functional blocks (not shown) to perform image encoding. The present invention can be applied to an image decoder in the same manner as that of the encoder.

As shown in FIG. 2, the data extraction and fitting apparatus according to the present invention includes a buffer 201, a register 202, a barrel shifter 203, a mask unit 204, a buffer 205, and a bit width information storage unit. 123, a bit width information extractor 210, an accumulator 220, a mask signal generator 230, and the like, store data input through the data bus in the buffer 201 and store the data in the buffer 201. After latching the data into the register 202, the data of the corresponding bit width is extracted according to the bit width information stored in the beep width information storage unit 123, and then fitted and stored in the RAM 124.

In FIG. 2, the buffer 201 is a first-in, first-out (FIFO) that sequentially stores and sequentially outputs input data in order to prevent data loss when a data transfer rate transmitted through the host bus is faster than a data extraction and fitting rate. Buffer, and the register 202 latches 16-bit multiplexed data and stores it until the extraction operation is completed.

The bit width information storage unit 123 stores information on the bit widths of the individual data contained in the multiplexed data input through the data bus in advance, and the information is extracted by the bit width information extractor 210 to accumulate ( 220 and the mask signal generator 230 is output.

The barrel shifter 203 has a window size of 8 bits and shifts the output of the register to the right by the bit input from the accumulator 220 so that the data to be extracted is always located on the right side.

At this time, in the embodiment of the present invention, the size of the multiplexed bit is 16 bits, the bit width of the individual data is limited to 1 to 8 bits, and the unit of bits processed in the system is 8 bits. Therefore, since the maximum bit of the individual data is 8 bits, 3 bits of bit information are required in order to express the bit width of 8 bits, and the barrel shifter 203, the mast unit 204, the buffer 205, and the like process 8 bits. It's enough if you can. If the maximum bit width of the individual data is 16 bits like the multiplexed bit width, the window of the barrel shifter is also 16 bits, and 4 bits are required to express the bit width information.

As described above, the technical idea of the present invention may be applied to data having an arbitrary bit length as it is, and therefore should not be construed as limited to the embodiments of the present invention.

The accumulator 220 is composed of an adder 221 and an accumulator register 222, as shown in FIG. 2, where the value of the accumulator register 222 is cleared to zero by a reset signal, and then the next cycle. From here, the output of the adder 221 is temporarily stored. The adder 221 adds the output of the bit width information extractor 210 and the previous value of the accumulator register and outputs the result to the accumulator register 222.

Accordingly, the barrel shifter 203 shifts the output of the register 202 to the right by the output of the accumulator 220. In the first cycle, since 0 is input, the barrel shifter 203 outputs the lower 8 bits as it is from the output of the register 202, and then from the accumulator. After shifting the register output to the right as much as the input value, the lower 8 bits are output.

As shown in FIG. 3, the mask signal generator 230 receives a decoder 232 for receiving and decoding bit information output from the bit width information extractor 210, and receives the output of the decoder and then decodes the lower bits. Is composed of a mask signal generation logic 234 for generating mask signals m0 to m7 with the output bits of 1 being 1 and the rest being 0. That is, the decoder 232 receives the bit width information of 3 bits to calculate the size of the bit width, and the mask signal generation logic 234 outputs 1 from the lower bits by the size of the bit width, and outputs 0 from the rest. .

In the embodiment of the present invention, when fitting individual data into 8 bits, data bits are inserted into the lower bits and the remaining upper bits are filled with 0. However, the output of the barrel shifter and the simple modification of the mask part place the data in the upper bits and lower You can also make the bit fill with zeros. As described above, the fitting result data is sorted by which one of ordinary skill in the art can easily design from an embodiment of the present invention.

As illustrated in FIG. 4, the mask unit 204 is implemented by eight end gates 204-1 through 204-8, and the mask signal generator (8) is output from 8-bit data output from the barrel shifter 203. According to the mask signals m0 to m7 output by the 230, the corresponding bits are output as they are, and the remaining bits are fitted to zero.

That is, when the mask signal m0 input to the first end gate 204-1 of the mask unit 204 is 1, the output of the barrel shifter is passed as it is (ie, D0 = D0 ′), but the mask signal m0 is If 0, 0 is output regardless of the output of the barrel shifter (i.e., D0 '= 0), and if the mask signal m1 input to the second end gate 204-2 is 1, the output of the barrel shifter is passed as it is ( That is, when D1 = D1 ') but the mask signal m1 is 0, 0 is output (i.e., D1' = 0) regardless of the output of the barrel shifter. If the mask signal m2 input to the third end gate 204-3 is 1, the output of the barrel shifter passes through as it is (i.e., D2 = D2 '), but if the mask signal m2 is 0, the barrel shifter outputs. Regardless, 0 is output (i.e., D2 '= 0), and when the mask signal m3 input to the fourth end gate 204-4 is 1, the output of the barrel shifter is passed as it is (i.e., D3 = D3' However, if the mask signal m3 is 0, 0 is output (ie, D3 '= 0) regardless of the output of the barrel shifter.

When the mask signal m4 input to the fifth end gate 204-5 of the mask unit 204 is 1, the output of the barrel shifter is passed as it is (that is, D4 = D4 '), but the mask signal m4 is If 0, 0 is output regardless of the output of the barrel shifter (i.e., D4 '= 0), and if the mask signal m5 input to the sixth end gate 204-6 is 1, the output of the barrel shifter is passed as it is ( That is, if D5 = D5 ') but the mask signal m5 is 0, 0 is output (i.e., D5' = 0) regardless of the output of the barrel shifter. If the mask signal m6 input to the seventh end gate 204-7 is 1, the output of the barrel shifter is passed as it is (ie, D6 = D6 '), but if the mask signal m6 is 0, the barrel shifter outputs. Regardless of whether 0 is output (ie, D6 '= 0) and the mask signal m7 input to the eighth end gate 204-8 is 1, the output of the barrel shifter is passed as it is (ie, D7 = D7' However, if the mask signal m7 is 0, 0 is output (ie, D7 '= 0) regardless of the output of the barrel shifter.

The buffer 205 temporarily stores the extracted and fitted data output by the mask unit 204 and outputs the data to the RAM 124. The RAM 124 is configured to buffer 205 according to a control signal of the RAM controller 125. Save the output of

Next, the operation of the above embodiment will be described in detail with reference to FIGS. 5 to 7.

5 is a view for explaining an example of the operation according to the present invention, Figure 6 is an example of a data format formed according to the data extraction operation result in the example shown in Figure 5, Figure 7 is an operation timing according to the present invention A timing diagram showing an example.

First, suppose that the 16-bit multiplexed data input in the embodiment of the present invention is combined into F1, F2, F3, F4, F5, and F6, as shown in Table 1 described above.

Then, the bit width information storage unit 123 stores bit width information for each individual data of the multiplexed 16 bit data. That is, since the bit widths from the F1 data to the F6 data are 3, 2, 5, 1, 4, 1, these values are stored in the bit width information storage unit 123.

As shown in FIG. 7, 16-bit multiplexed data is stored in the register 202 by the latch clock, and the accumulator register 222 is cleared by the reset signal so that the output of the accumulator 220 is zero. Becomes The bit width information extractor 210 extracts the bit width value 3 ₁₀ of the F1 data stored in the bit width information storage unit 123 and outputs the bit width value 3 ₁₀ to the accumulator 220 and the mask signal generator 230. At this time, 3 ₁₀ is input to the accumulator 220, but 0 stored in the register 222 of the accumulator is output in the first cycle, and 0 stored in the register 222 of the accumulator and 3 input to the accumulator are added in the next cycle. (= 3 + 0) is stored in register 222 and this value is output.

The mask signal generator 230 receives 3 ₁₀ from the bit width information extractor 210 and decodes the decoder 232, and then sets the mask signal generation logic 234 to 1 from the lower bits, and the rest to 0. The mask signals m0 to m7 are generated. For example, when 3 is input, a mask signal of m0 = 1, m1 = 1, m2 = 1, m3 = 0, m4 = 0, m5 = 0, m6 = 0, m7 = 0 is generated and output.

The barrel shifter 203 shifts 16-bit data stored in the register 202 by '0' outputted by the register 222 of the accumulator, and then lower 8 bits (that is, 3 bits of F1, 2 bits of F2, and 3 bits of F3). )

The mask unit 204 outputs 3 bits of F1 data as it is from the 8-bit output of the barrel shifter 203 according to the mask signals m0 to m7, and fits the remaining 5 bits to zero.

After the extraction and fitting of the F1 data is completed in this manner, the extraction and fitting of the F2 data are performed.

That is, the bit width information extractor 210 extracts 2, which is the bit width value of the F2 data after 3, and outputs the result to the accumulator 220 and the mask signal generator 230, and the accumulator 220 receives 3 and 0 previously input. This added result prints the value of the stored register (that is, 3) and receives 2. The mask signal generator 230 receives and decodes 2, and then decodes a mask signal having m0 = 1, m1 = 1, m2 = 0, m3 = 0, m4 = 0, m5 = 0, m6 = 0, and m7 = 0. Generate and print.

The barrel shifter 203 shifts the 16-bit data stored in the register 202 right by '3 bits outputted by the register of the accumulator' and then lower 8 bits (that is, 2 bits of F2, 5 bits of F3, and 1 bit of F4). Outputs

The mask unit 204 outputs two bits of F2 data as it is in accordance with the mask signals m0 to m7 from the eight-bit output of the barrel shifter, and fits the remaining six bits to zero.

After the extraction and fitting of the F2 data is completed in this manner, the extraction and fitting of the F3 data are performed.

That is, the bit width information extractor 210 extracts 5, which is a bit width value of F3 data after 2, and outputs the result to the accumulator 220 and the mask signal generator 230, and the accumulator 220 is 2 and 3 previously input. The added result 5 outputs the value of the stored register and receives F3 bit width information 5. The mask signal generator 230 receives and decodes 5 and decodes a mask signal having m0 = 1, m1 = 1, m2 = 1, m3 = 1, m4 = 1, m5 = 0, m6 = 0, m7 = 0. Generate and print.

The barrel shifter 203 shifts the 16-bit data stored in the register 202 right by '5 bits outputted by the accumulator' and then shifts the lower 8 bits (that is, F3 5 bits, F4 1 bit, and F5 2 bits). Output

The mask unit 204 outputs 5 bits of F3 data as it is from the 8-bit output of the barrel shifter 203, in accordance with the mask signals m0 to m7, and fits the remaining 3 bits to zero.

In this way, when extraction and fitting of the F3 data is completed, extraction and fitting of the F4 data are then performed.

That is, the bit width information extractor 210 extracts 1, which is a bit width value of F4 data after 5, and outputs the result to the accumulator 220 and the mask signal generator 230, and the accumulator 220 accumulates 5 previously inputted. As a result of adding 5, 10 ₁₀ outputs the value of the stored register 222 and receives F4 bit width information 1. The mask signal generator 230 receives and decodes 1, and then decodes a mask signal having m0 = 1, m1 = 0, m2 = 0, m3 = 0, m4 = 0, m5 = 0, m6 = 0, and m7 = 0. Generate and print.

The barrel shifter 203 shifts the 16-bit data stored in the register 202 right by '10 bits outputted by the accumulator 'and then lower 8 bits (ie, F4 1 bit, F5 4 bit, F6 1 bit, 0). 2 bits). In the case where the barrel shifter has a ring structure, F1 data is reconnected after F6 data during the right shift operation. However, in the embodiment of the present invention, the empty space is filled with zero after F6 data.

The mask unit 204 outputs one bit of F4 data as it is in accordance with the mask signals m0 to m7 from the eight-bit output of the barrel shifter, and fits the remaining seven bits to zero.

Subsequently, when extraction and fitting of the F4 data are completed, extraction and fitting of the F5 and F6 data are performed in the same manner as described above.

When both extraction and fitting of the multiplexed 16-bit data are performed in this manner, as shown in FIG. 6, eight bytes of data including F1 to F6 data are formed, and the result is the result of the RAM controller 125. It is stored in the RAM 124 and processed according to the control.

7 is an operation timing diagram of an embodiment according to the present invention. After 16-bit multiplexed data is latched according to a latch clock, processing is performed sequentially according to bit width information (3, 2, 5, 1, 4, 1). To show that individual data (F1, F2, F3, F4, F5, F6) is output.

After the extraction and fitting operations for the 16-bit multiplexed data are completed, the next multiplexed 16-bit data is latched and processed in the same manner as described above.

As described above, the present invention can easily process data by inputting the bit width information stored in advance, extracting a corresponding data portion from the multiplexed data using a barrel shifter to a predetermined length, and fitting the mask portion to form individual data. Can be.

Claims (6)

Receiving data obtained by multiplexing at least one individual data, receiving bit width information from a bit width information storage unit in which information on the bit width of the individual data is stored in advance, extracting the individual data, and fitting the predetermined length In the data extraction and fitting apparatus for A register 202 for latching and storing multiplexed data of a predetermined size; Bit width information extracting means (210) for sequentially outputting bit width information stored in the bit width information storage unit; An accumulator 220 which receives bit width information from the bit width information extracting means and accumulates its output; Mask signal generating means (230) for receiving bit width information from said bit width information extracting means and generating a mask signal; A barrel shifter (203) for outputting data of a predetermined size by shifting data stored in the register according to the output of the accumulator; And And masking means (204) for fitting data by masking the output of the barrel shifter according to the mask signal. The data extraction and fitting apparatus of claim 1, wherein the data extraction and fitting apparatus further comprises a buffer for preventing loss of the multiplexed data when the input speed of the multiplexed data is faster than the extraction and fitting processing speed. Device. 2. The apparatus of claim 1, wherein the accumulator (220) comprises an adder (221) and an accumulator register (222) for clearing according to a reset signal and storing the output of the adder. 2. The apparatus of claim 1, wherein the mask signal generating means comprises a decoder for receiving and decoding the bit width information, and a mask signal generation logic for generating a mask signal according to the output of the decoder. . The data extracting and fitting of claim 1, wherein the masking means comprises a plurality of end gates that output the barrel shifter as it is when the mask signal is 1 and output 0 when the mask signal is 0. Device. In a video encoding / decoding system wherein a host controller and an image encoding device are connected by a host bus and image-code the data input through a data bus on the host bus under the control of the host controller. The video encoding apparatus A bus matching unit for converting a virtual address input through the host bus into a physical address and connecting data; A bit width information storage unit which stores bit width information of individual data included in the multiplexed and input data in advance; A data extraction and fitting unit which receives the multiplexed data input through the bus matching unit, extracts the individual data according to the bit width information output by the bit width information storage unit, and then fits and fits the fixed length data of a predetermined size; And And a RAM configured to store an output of the data extraction and fitting unit under control of a RAM controller.