KR930007199B1 - Manufacturing method of planar type capacitor - Google Patents

Manufacturing method of planar type capacitor Download PDF

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KR930007199B1
KR930007199B1 KR1019900012459A KR900012459A KR930007199B1 KR 930007199 B1 KR930007199 B1 KR 930007199B1 KR 1019900012459 A KR1019900012459 A KR 1019900012459A KR 900012459 A KR900012459 A KR 900012459A KR 930007199 B1 KR930007199 B1 KR 930007199B1
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film
ono
etching
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oxide
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KR920005388A (en
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이상래
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
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Abstract

The flattened capacitor for MOS memory device is mfd. by (a) depositing an oxide-nitride-oxide (ONO) film (22) and a polycrystalline silicon film (23) on the silicon substrate (1) in order, (b) doping an impurity on the silicon film (23), (c) ion-implanting an impurity into the film (23), (d) slant-etching the fixed part of the film (23) to expose the ONO film (22), (e) oxidizing the polysilicon to form an oxide film (25) on the film (23), (f) growing the film (25), and then lifting off the exposed film (22) by the dry etching method.

Description

평판형 커패시터 제조방법Method of manufacturing flat capacitor

제1도는 종래의 공정단면도.1 is a conventional cross-sectional view of the process.

제2도는 본 발명의 공정단면도.2 is a cross-sectional view of the process of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 22 : ONO막1: silicon substrate 22: ONO film

23 : 다결정실리콘막 24 : 감광제23 polycrystalline silicon film 24 photosensitive agent

25 : 산회막25: acid film

본 발명은 평판형 커패시터 제조방법에 관한 것으로, 특히 범용의 MOS(Metal Oxide Semiconguctor)기억소자에 적당하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar capacitor manufacturing method, and particularly, to be suitable for general-purpose MOS (Metal Oxide Semiconguctor) memory devices.

종래의 DRAM(Dynamic Random Access Memory)소자의 핵심부위인 평판형 커패시터(Planar Capacitor)제조공정을 첨부된 제1도(a) 내지 (h)를 참조하여 상술하면 다음과 같다.A planar capacitor manufacturing process, which is a core part of a conventional DRAM (Dynamic Random Access Memory) device, will be described in detail with reference to FIGS. 1A through 1H.

먼저 (a)와 같이 게이트(3), 소오스/드레인(4)등으로 이루어진 트랜지스터가 형성된 실리콘기판(1)위에 (미설명부호 2는 필드산화막, 5는 측벽스페이서이다)First, on (a) a silicon substrate 1 on which a transistor composed of a gate 3, a source / drain 4, etc. is formed (not shown 2 is a field oxide film, 5 is a sidewall spacer).

유전체절연막으로서 ONO(Oxide

Figure kpo00002
Nitride
Figure kpo00003
Oxide)막(12)(또는 NO막)을 형성하고 (b)와 같이 다결정실리콘막(13)을 증착한 다음 이 다결정실리콘막(13)이 전도성을 갖도록 N타입 불순물을 주입한다.ONO (Oxide) as dielectric insulating film
Figure kpo00002
Nitride
Figure kpo00003
An oxide film 12 (or NO film) is formed, and a polysilicon film 13 is deposited as shown in (b), and then an N-type impurity is implanted so that the polycrystalline silicon film 13 is conductive.

이 N타입 불순물 주입은 일반적으로 인글래스처리(POCl3도핑)에 의해 실시되며 이온주입방법으로도 행하여진다. 이때 인글래스처리를 하는 경우에는 인글래스층(P2O5)이 생성되는데 이는 불화수소(HF)용액으로 제거한다.This N-type impurity implantation is generally performed by inglass treatment (POCl 3 doping) and also by an ion implantation method. At this time, when the glass is subjected to the in-glass layer (P 2 O 5 ) is generated, which is removed with a hydrogen fluoride (HF) solution.

그리고 (c)와 같이 산화막(14)을 형성한 다음 (d)와 같이 감광제(15) 도포, 노광, 현상의 마스킹 공정을 거쳐(e)와 같이 감광체(15)를 마스크로하여 상기 증착된 산화막(14)을 불화수소(HF)용액을 사용한 습식식각법으로 경사식각한 다음 곧이어 (f)와 같이 건식식각 장비로서 상기 다결정실리콘막(13)을 식각한다.Then, the oxide film 14 is formed as shown in (c), and then the photosensitive material 15 is masked through the masking process of applying, exposing and developing the photosensitive agent 15 as shown in (d). (14) is obliquely etched by a wet etching method using hydrogen fluoride (HF) solution, and then the polysilicon film 13 is etched as a dry etching equipment as in (f).

이어 (g)와 같이 유전체 절연막으로 사용된 ONO막(12)을 제거하여 단결정실리콘기판(11)을 오픈시킨다음(h)와 같이 상기 감광제(15)를 제거하므로써 ONO막(12)과 다결정실리콘막(13) 및 산화막(14)으로 이루어진 평판형 커패시터 제조공정이 완료된다.Then, as shown in (g), the ONO film 12 used as the dielectric insulating film is removed to open the single crystal silicon substrate 11, and as shown in (h), the photosensitive agent 15 is removed to remove the ONO film 12 and the polycrystalline silicon. The flat capacitor manufacturing process consisting of the film 13 and the oxide film 14 is completed.

그러나 상기 종래 기술은 한층의 감광제(15)를 마스크로 하여 여러층의 막을 식각하게 되므로 감광제(15)의 형상손상을 가져올 뿐만아니라 먼지 발생의 가능성이 높다는 단점이 있었다.However, the prior art has a disadvantage in that a plurality of layers of the photoresist is etched using a single photosensitive agent 15 as a mask, resulting in a shape damage of the photosensitive agent 15 and a high possibility of dust generation.

또한 다결정실리콘막(13)의 경사식각이 어렵다는 단점이 있었다. 본 발명은 상기 단점을 제거키 위한 것으로 공정을 감소시켜 단축 및 제조원가를 낮출 수 있고 소지의 정합특성을 향상시켜 신뢰성을 증가시킬 수 있는 방법을 제공하는데 그 목적이 있다.In addition, there was a disadvantage that the oblique etching of the polysilicon film 13 was difficult. SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above disadvantages, and the object of the present invention is to provide a method of reducing the process, reducing the manufacturing cost and improving the matching property of the base to increase the reliability.

상기 목적을 달성하기 위한 수단으로서 본 발명은 평판형 커패시터 제조공정에 있어서, 실리콘기판(1)위에 ONO막(22)과 다결정실리콘막(23)을 차례로 증착하는 단계, 상기 다결정실리콘막(23)에 불순물을 도핑하는 단계, 상기 다결정실리콘막(23)에 불순물을 이온 주입하는 단계, 상기 다결정실리콘막(23)의 소정 부분을 경사 식각하여 상기 ONO막(22)을 노출시키는 단계, 결과물을 선택적 산화시키는 단계 노출된 상기 ONO막(22)을 식각하는 단계가 순차적으로 구비된 것이다.As a means for achieving the above object, the present invention provides a step of sequentially depositing an ONO film 22 and a polysilicon film 23 on a silicon substrate 1 in the plate capacitor manufacturing process, the polysilicon film 23 Doping impurities into the polycrystalline silicon film 23; implanting impurities into the polysilicon film 23; exposing the ONO film 22 by oblique etching a predetermined portion of the polysilicon film 23; Oxidation Etching the exposed ONO film 22 is sequentially performed.

이를 일실시예인 DRAM소자의 핵심부위인 커패시터 형성 공정을 나타내는 첨부된 제2도(a) 내지(g)를 참조하여 상술하면 다음과 같다.This will be described below with reference to the accompanying drawings (a) to (g) of FIG. 2, which illustrate a capacitor forming process, which is a core part of a DRAM device.

먼저 (a)와 같이 게이트(3), 소오소/드레인(4)으로 이루어진 트랜지스터가 형성된 실리콘기판(1)위에 20-50Å 두께의 산화막과 50-150Å 두께의 질화막 및 200-2000Å두께의 산화막을 차례로 증착한 ONO막(또는 NO막)(22)을 유전층으로서 형성하고 (b)와 같이 다결정실리콘막(23)을 2000-4000Å의 두께로 증착한다.First, as shown in (a), an oxide film having a thickness of 20-50 Å, a nitride film having a thickness of 50-150 및, and an oxide film having a thickness of 200-2000 에 is formed on the silicon substrate 1 on which a transistor composed of a gate 3 and a source / drain 4 is formed as shown in (a). A sequentially deposited ONO film (or NO film) 22 is formed as a dielectric layer, and the polysilicon film 23 is deposited to a thickness of 2000-4000 mm as shown in (b).

이때, 상기 ONO막중에서 질화막은 질화막 증착 공정 또는 열반응에 의한 질화막 성장 공정에 의해 형성한다. 이어서 상기 형성된 다결정실리콘막(23)이 전도성을 갖도록 POCl3를 도핑한다. 이때 인글래스층(P2O5)이 생성되게 되는데 이 인글래스층을 불화수소(HF)용액으로서 제거한 다음, 계속해서 이온 주입 공정에 의해 As불순물을 1015정도의 도핑농도로 상기 다결정 실리콘막(23)에 얕게 주입시킨다.At this time, in the ONO film, the nitride film is formed by a nitride film deposition process or a nitride film growth process by thermal reaction. Subsequently, the polysilicon film 23 formed is doped with POCl 3 to have conductivity. In this case, an inglass layer (P 2 O 5 ) is formed, and the inglass layer is removed as a hydrogen fluoride (HF) solution, and then the polycrystalline silicon film is removed at a doping concentration of about 10 15 by an ion implantation process. Inject shallowly into (23).

이때의 주입에너지는 20-40KeV로 조절하여 주입한다. 이 공정은 상기 다결정실리콘막(23)의 표면부위를 인위적으로 격지 손상시켜 이후 진행되는 다결정실리콘막(3)의 식각시 경시식각 특성을 향상시키기 위한 것이다.At this time, the injection energy is adjusted to 20-40KeV. This step is to artificially damage the surface portion of the polysilicon film 23 to improve the time-lapse etching characteristics during the etching of the polysilicon film 3 to be subsequently performed.

이어 (c)와 같이 감광제(24)의 도포의 노광 및 현상을 거쳐 마스크를 형성한 후(d)와 같이 다결정실리콘막(23)을 경시식각하는바, 표면부위가 손상되어 있기 때문에 하부보다 표면부위의 식각이 잘 진행되므로 수월하게 경시식각을 행할 수 있다. 이상과 같이 다결정실리콘막(23)을 경시식각한 후 (e)와 같이 감광제(24)를 벗겨내고 선택된 산화 공정을(f)와 같이 실시한다.Subsequently, after forming the mask through exposure and development of the application of the photosensitive agent 24 as shown in (c), the polysilicon film 23 is etched over time as shown in (d). Etching of the site proceeds well, so it can be easily time-lapsed etching. After the polysilicon film 23 is etched over time as described above, the photosensitive agent 24 is peeled off as shown in (e), and the selected oxidation process is performed as shown in (f).

이 선택적 산화는 질화막위에서는 산화막이 형성되지 않는다는 특성을 이용한 것으로 상기 경시 식각된 다결정실리콘을 산화시키면 다결정실리콘(23)위에는 산화막(25)이 형성되나 노출된 ONO(Oxide-Nitride-Oxide)(또는 NO막)(22)상에는 질화막(Nitride)으로 인해 산화막이 형성되지 않는다.This selective oxidation utilizes the property that an oxide film is not formed on the nitride film. When the etched polycrystalline silicon is oxidized over time, an oxide film 25 is formed on the polycrystalline silicon 23, but the exposed ONO (Oxide-Nitride-Oxide) (or On the NO film 22, an oxide film is not formed due to a nitride film.

이때 상기 산화막(25)은 2000Å-4000Å의 두께가 되도록 성장시킨다. 이어(g)와 같이 실리콘기판(1)위의 노출된 상기 ONO막(또는 NO 막)(22)를 건식 식각법으로 제거함으로써, ONO막(22)과 플레이트전극이 되는 다결정실리콘막(23) 및 산화막(25)으로 이루어진 평판형 커패시터를 완성한다. 이때의 건식 식각은 표면손상을 최소화하기 위해 다운 스트림형 식각장치(플라즈마 생성실이 웨이퍼와 떨어져 있는 식각장치)를 이용하여 제거하는 것이 유리하다.At this time, the oxide film 25 is grown to have a thickness of 2000 kPa-4000 kPa. Then, by removing the ONO film (or NO film) 22 exposed on the silicon substrate 1 by dry etching as shown in (g), the polysilicon film 23 serving as the ONO film 22 and the plate electrode 23 is formed. And a planar capacitor composed of an oxide film 25. At this time, the dry etching is advantageously removed using a downstream etching apparatus (an etching apparatus in which the plasma generating chamber is separated from the wafer) in order to minimize surface damage.

또한 ONO막(22)을 습식 식각에 의해 제거하는 것도 가능하다. 이상과 같이 본 발명에 의하면 다음과 같은 효과가 있다.It is also possible to remove the ONO film 22 by wet etching. As described above, the present invention has the following effects.

첫째, 선택적 산화막 형성에 의한 공정유지보수성을 향상시킬 수 있고, 소지의 정합 특성을 소지의 신뢰성을 증대시킬 수 있다. 둘째, 공정을 감소시켜 공기를 단축시키고 제조원가를 낮출 수 있다.First, process maintenance can be improved by forming a selective oxide film, and the matching property of the base can be increased by the reliability of the base. Second, the process can be reduced to shorten the air and lower the manufacturing cost.

Claims (7)

실리콘기판(1)위에 ONO막(22)과 다결정실리콘막(23)을 차례로 증착하는 단계, 상기 다결정실리콘막(23)에 불순물을 도핑하는 단계, 상기 다결정실리콘막(23)에 불순물을 이온 주입하는 단계, 상기 다결정실리콘막(23) 소정 부분을 경사 식각하여 상기 ONO막(22)을 노출시키는 단계, 결과물을 선택적 산화시키는 단계, 노출된 상기 ONO막(22)을 식각하는 단계가 순차적으로 구비됨을 특징으로 하는 평판형 커패시터 제조방법.Depositing the ONO film 22 and the polycrystalline silicon film 23 on the silicon substrate 1 in order, doping the polysilicon film 23 with impurities, and implanting impurities into the polysilicon film 23. And exposing the ONO film 22 by obliquely etching a predetermined portion of the polysilicon film 23, selectively oxidizing a resultant, and etching the exposed ONO film 22. Flat capacitor manufacturing method characterized in that. 제1항에 있어서, ONO막(22)대신에 NO막을 형성함을 특징으로 하는 평판형 커패시터 제조방법.The method of claim 1, wherein an NO film is formed in place of the ONO film (22). 제1항에 있어서, ONO막(22)은 20-50Å 두께의 산화막과 50-150Å두께의 절화막, 200Å-2000Å 두께의 산화막을 차례로 성장 및 증착하여 형성함을 특징으로 하는 평판형 커패시터 제조방법.The method of claim 1, wherein the ONO film 22 is formed by sequentially growing and depositing an oxide film having a thickness of 20-50 kHz, a cut film having a thickness of 50-150 ,, and an oxide film having a thickness of 200 Å-2000 Å. . 제1항에 있어서, 상기 불순물을 도핑하는 단계는 POCl3도핑한 후 이때 생성되는 인글래스층을 불화수소(HF)용액으로 제거하는 공정에 의해 행해짐을 특징으로 하는 평판형 커패시터 제조방법.The method of claim 1, wherein the doping of the impurity is performed by removing a glass layer produced by hydrogen fluoride (HF) solution after doping POCl 3 . 제1항에 있어서, 상기 불순물을 이온 주입하는 단계는 As를 1015도핑농도로 20-40KeV의 에너지에 의해 이온주입함으로써 행해짐을 특징으로 하는 평판형 커패시터 제조방법.The method of claim 1, wherein the implanting of the impurities is performed by ion implantation of As into a 10 15 doping concentration with an energy of 20-40 KeV. 제1항 및 제3항에 있어서, 상기 ONO막(22)중 질화막은 질화막 증착공정 또는 열반응에 의한 질화막 성장공정으로 형성함을 특징으로 하는 평판형 커패시터 제조방법.The method of claim 1 or 3, wherein the nitride film in the ONO film (22) is formed by a nitride film deposition process or a nitride film growth process by thermal reaction. 제1항에 있어서, 상기 ONO막(22)의 식각은 건식 식각법 또는 습식식각법으로 행하는 것을 특징으로 하는 평판형 커패시터 제조방법.The method of claim 1, wherein the etching of the ONO film (22) is performed by a dry etching method or a wet etching method.
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