KR930007104A - Voltage level shift digital / analog conversion circuit - Google Patents

Voltage level shift digital / analog conversion circuit Download PDF

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Publication number
KR930007104A
KR930007104A KR1019910017111A KR910017111A KR930007104A KR 930007104 A KR930007104 A KR 930007104A KR 1019910017111 A KR1019910017111 A KR 1019910017111A KR 910017111 A KR910017111 A KR 910017111A KR 930007104 A KR930007104 A KR 930007104A
Authority
KR
South Korea
Prior art keywords
voltage level
conversion circuit
digital
analog conversion
buffer
Prior art date
Application number
KR1019910017111A
Other languages
Korean (ko)
Inventor
최의섭
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910017111A priority Critical patent/KR930007104A/en
Priority to JP4061723A priority patent/JPH05136696A/en
Publication of KR930007104A publication Critical patent/KR930007104A/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

본 발명은 디지탈/아날로그 변환회로로서, 다수의 스위치와 다수의 캐패시터 및 버퍼로 이루어진 디지탈/아날로그 변환회로에 있어서, 상기 버퍼의 비반전단자에 전압레벨을 결정하고 버퍼의 오프셋전압을 제거하는 전압레벨쉬프트 및 오프셋전압 제거회로를 연결함과 더불어 상기 버퍼 반전단자와 출력단 사이에 캐패시터를 병렬로 연결하여 캐패시터의 수효를 줄여 디지탈/아날로그 변환회로의 전체면적을 최소화하는 전압레벨쉬프트 디지탈/아날로그 변환회로이다.The present invention relates to a digital / analog conversion circuit comprising a plurality of switches, a plurality of capacitors, and a buffer, wherein the voltage level determines a voltage level at a non-inverting terminal of the buffer and removes the offset voltage of the buffer. A voltage level shift digital / analog conversion circuit that minimizes the total area of the digital / analog conversion circuit by reducing the number of capacitors by connecting a capacitor in parallel between the buffer inverting terminal and the output terminal. .

Description

전압레벨쉬프트 디지탈/아날로그 변환회로Voltage level shift digital / analog conversion circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명 전압레벨쉬프트 디지탈/아날로그 변환회로의 개략적인 구성도,2 is a schematic configuration diagram of a voltage level shift digital / analog conversion circuit of the present invention;

제4도는 본 발명 전압레벨쉬프트 디지탈/아날로그 변환회로의 비트증가에 따른 출력전압과 각 레벨을 나타낸 그래프.4 is a graph showing the output voltage and each level according to the bit increase of the voltage level shift digital / analog conversion circuit of the present invention.

Claims (2)

다수의 스위치와 다수의 캐패시터 및 버퍼(1)로 이루어진 디지탈/아날로그변환회로에 있어서, 상기 버퍼(1)의 비반전단자(+)에 전압레벨을 결정하고 버퍼(1)의 오프셋전압을 제거하는 전압레벨쉬프트 및 오프셋전압 제거회로(2)를 연결함과 더불어 상기 버퍼(1) 반전단자(-)와 출력단(OUT) 사이에 캐패시터(S1∼S4)를 병렬로 연결하여 캐패시터의 수효를 줄여 디지탈/아날로그 변환회로의 전체면적을 최소화함을 특징으로 하는 전압레벨쉬프트 디지털/아날로그변환회로.In a digital / analog conversion circuit composed of a plurality of switches, a plurality of capacitors, and a buffer (1), the voltage level is determined at the non-inverting terminal (+) of the buffer (1) and the offset voltage of the buffer (1) is removed. In addition to connecting the voltage level shift and offset voltage removing circuit 2, the capacitors S 1 to S 4 are connected in parallel between the inverting terminal (-) and the output terminal (OUT) of the buffer (1) to increase the number of capacitors. A voltage level shift digital / analog conversion circuit, characterized in that to minimize the total area of the digital / analog conversion circuit. 제1항에 있어서, 상기 디지탈/아날로그변환회로(DAC)가 하위(n-m-1) 비트에서 최하위비트(LSB)까지의 디지탈 신호를 아날로그 신호로 변환하고, 상위(n-1) 비트에서 (n-m) 비트까지의 디지탈신호를 전압레벨쉬프트 및 오프셋전압 제거회로(2)를 통해 버퍼(1)의 비반전단자(+)에 가하여 전압레벨을 조정함으로써 n 비트의 디지탈 신호를 아날로그신호로 변환함을 특징으로 하는 전압레벨쉬프트 디지탈/아날로그 변환회로.The digital-to-analog conversion circuit (DAC) of claim 1 converts a digital signal from a lower (nm-1) bit to a least significant bit (LSB) into an analog signal, and converts a (nm) signal from an upper (n-1) bit to (nm). ) N digital signals are converted into analog signals by adjusting the voltage level by applying the digital signal up to the bit to the non-inverting terminal (+) of the buffer (1) through the voltage level shift and offset voltage removing circuit (2). A voltage level shift digital / analog conversion circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910017111A 1991-09-30 1991-09-30 Voltage level shift digital / analog conversion circuit KR930007104A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019910017111A KR930007104A (en) 1991-09-30 1991-09-30 Voltage level shift digital / analog conversion circuit
JP4061723A JPH05136696A (en) 1991-09-30 1992-03-18 Voltage level shift digital/analogue converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910017111A KR930007104A (en) 1991-09-30 1991-09-30 Voltage level shift digital / analog conversion circuit

Publications (1)

Publication Number Publication Date
KR930007104A true KR930007104A (en) 1993-04-22

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ID=19320568

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910017111A KR930007104A (en) 1991-09-30 1991-09-30 Voltage level shift digital / analog conversion circuit

Country Status (2)

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JP (1) JPH05136696A (en)
KR (1) KR930007104A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227283A (en) 1995-02-21 1996-09-03 Seiko Epson Corp Liquid crystal display device, its driving method and display system
JP2001111427A (en) 1999-10-05 2001-04-20 Nec Corp Switched capacitor type digital/analog converter

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0205723B1 (en) * 1985-06-28 1988-09-14 Franz Plasser Bahnbaumaschinen-Industriegesellschaft m.b.H. Mobile track-working machine and method for bending the ends of laid rails in the joint zone
JPS6276822A (en) * 1985-09-30 1987-04-08 Kenzo Watanabe Digital analog converting method
DE3587950T2 (en) * 1985-12-30 1995-05-24 Ibm Parallel algorithmic digital / analog converter.

Also Published As

Publication number Publication date
JPH05136696A (en) 1993-06-01

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