KR930007042B1 - Circuit for generating byte validity signal in memory access circuit - Google Patents

Abstract

The type valid signal generating circuit generating a signal for designating size and position of byte, halfword and word according to byte address designating signal and big endian/little endian byte selection signals. The circuit comprises an input stage comprising inverters (I1-I4), NOR gates (N1-N4), and 4-input 1- output multiplexers (1-4) for designating byte size according to byte address designating signals (A0,A1) and big endian/little endian bus selection signal (BLB), an exclusive OR and an exclusive NOR gate (EX1,EX2) for designating byte size for halfword request signal input, multiplexers (5-8) for generating size of byte, halfword, and word for memory access request signal, and a multiplexer (S) for outputting data byte request signal (DBE) according to pixel instruction address selection signal (IPST) and output signals of the multiplexers (5-8).

Description

Byte Valid Signal Generation Circuit in Memory Access Circuit

1 is a circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1, 2, 3, 4, 9: 2 input 1 output multiplexer 5, 6, 7, 8: 4 input 1 output multiplexer

EX1: Exclusive OR Gate EX2: Exclusive NOR Gate

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a byte valid signal generation circuit in a memory access circuit for specifying the size and position of bytes, halfwords, and words in a memory access circuit of a 32-bit microprocessor.

In general, it is already known that in a microprocessor system, the size of a data bus is set to 32 bits and 8 bits, 16 bits, and 32 bits of data are defined as bytes, halfwords, and words, respectively.

In the conventional 32-bit microprocessor system, however, the address value of the register is determined only when necessary without setting the size according to the address values of bytes, halfwords, and words in the registers. In other words, the design of the bus is complicated and the control signals for using the bus are complicated.

Accordingly, an object of the present invention is to provide a byte valid signal generation circuit in a memory access circuit in which a 32 bit microprocessor outputs a signal for determining an effective size and an effective position based on the byte data valid signal. .

To this end, the present invention uses a 32-bit microprocessor as a byte addressing signal input and outputs a signal specifying the size and position of bytes, halfwords, and words according to the state of the big endian / little endian byte selection signal. will be.

The present invention will be described in detail with reference to the accompanying drawings as follows.

The byte addressing signal A0 is applied to one side and the other side of the NOR gates N1 (N2) (N3) and N4 directly or via an inverter I1 (I2) I4, and the byte addressing signal ( A1 is applied to the other side and one side of the NOR gates N1, N2, N3, and N4 directly or via an inverter I3, and at the same time to the exclusive OR gate EX1 and one side of the exclusive NOR gate EX2. The output of the NOR gate N1 is supplied to one input terminal A and the other input terminal B of the two input one output multiplexer 1 and 4, and the output of the NOR gate N2 is two input one. The output of the NOR gate N3 is connected to one input terminal A and the other input terminal B of the output multiplexers 2 and 3 and the other input terminal B of the two input one output multiplexer 2 and 3, respectively. At one input terminal (A), the output of the NOR gate (N4) is input to the other input terminal (B) and input terminal (A) of the two input one output multiplexer (1), (4), respectively, big endian / little end Unbus structure designation signal (Big en A dian little endian bar (BLB) is applied to the other side of the exclusive OR gate EX1 and the exclusive NOR gate EX2 while being applied to the selection terminal S of the two input one output multiplexers 1 to 4. The ground potential GND, which is a low potential (0), is supplied to the input terminal D0 of the four-input one-output multiplexer (5), (6), (7), and (8). PWR is applied simultaneously to the input terminal D3, and the outputs of the two-input one-output multiplexers 1 to 4 pass through inverts I5, I6, I7, and I8, respectively. The inputs D1 of the four input one output multiplexers 5 to 8 are respectively inputted, and the output of the exclusive NOR gate EX2 is input to the four input one output multiplexers 5 and 6, respectively. The output of the exclusive OR gate EX2 to the input terminal D2 of the 4-input one-output multiplexer 5, 6 at D2), and the output of the exclusive OR gate EX1 is the 4-input one-output multiplexer 7 at D2). To the input terminal D2 of (8), The outputs of the four input one-output multiplexers 5 to 8, in which the memory access request signal WB and the half word or more memory access request signals WH are input to the two selection terminals A and B, respectively, are two. To the input terminal A of the input 1 output multiplexer P, and the byte address supply signals RC, 3... 0>) and the second input 1 output multiplexer 9 connected to the output terminal Q and the other input terminal B of the flip-flop 10 into which the clock pulse CLK is input to the input terminal D and the clock terminal, respectively. A pixel command address selection signal IPST is applied to the terminal S so that a 4-bit data byte enable signal DBE is output from the output terminal thereof through the inverter I9. will be.

The byte valid signal generation circuit of the present invention constructed as described above specifies the byte address when the big endian bus structure is selected, that is, when the big endian / little endian bus structure designation signal BLB is inputted with "1". As the signals A1 and A0 are input as 00,01,10,11, the data byte valid signals DBE0, DBE1, DBE2, and DBE3 are activated as valid signals, respectively, and the little endian structure is selected. If the byte address designation signals A1 and A0 are inputted as 00,01,10,11, the data byte valid signals DBE3, DBE2, DBE1, and DBE0 are activated as valid signals, respectively.

If the big endian bus structure is selected and the halfword request is made, as the byte address designation signal A1 is inputted as 0 and 1, the data byte valid signals DBE2 and DBE3 are activated as valid signals, respectively. If is selected and the halfword request, the data byte valid signals DBE2, DBE3, and DBE0, DBE1 are respectively activated as valid signals as the byte address designation signal A1 is inputted as 0,1.

In addition, if both the big endian and the little endian are word requests, all of the data valid signals DBE3, DBE2, DBE1, and DBE0 are activated. All are deactivated to zero.

If it is not a memory cycle request, the memory access request signal WB having a byte size and the memory access request signal WH equal to or greater than half word are inputted as 00, so that the input terminal D0 of the four input one output multiplexers 5 to 8 is input. With this selected, ground GND is applied to one input terminal A of the two-input one-output multiplexer 9, and the pixel command address selection signal IPST is inputted as zero, thereby enabling the data byte valid signals DBE3, DBE2, DBE1, and DBE0. ) Are all output as 0.

In the case of a word request, since the above-mentioned memory access request signal WB having a byte size and a half word or more memory access request signal WH are input to 1, 1, the power byte PWR is selected and the data byte request signal ( DBE3, DBE2, DBE1, DBE0) are all 1's output.

When the byte address designation signals A1 and A0 are input to 11 during byte access, they are output as 0,0, 0,1 from the NOR gates N1 to N4 via the inverters I1 to I4, and the two input one output multiplexer. (1) Only one is input to the other input terminal (B) and one input terminal (A) of (4), and in the case of a big-endian bus structure, the big-endian / little-endian bus structure designation signal (BLB) is set to 1 Since 1 is inputted only to the input terminal D1 of the 4-input 1-output multiplexer 5, and since the byte access, only the memory access request signal WB of byte size is 1, and the 4-input 1-output multiplexer 5 to 6 is inputted. Is applied to the input terminal A of the two-input one-output multiplexer 9 and input as 1,0, 0, 0 so that the data byte valid signals DBE0, DBE1, DBE2, and DBE3 are 1, By outputting 0, 0, 0, only the byte corresponding to bit 7 of bit 7 of the actual bus is selected.

On the other hand, if the little endian, the big endian / little endian bus structure designation signal (BLB) is inputted as 0, and one input terminal of the four input one output multiplexers 1 to 4 is selected and the four input one output multiplexer 5 Outputs 0,0, 0,1 of) to (8) output the data byte valid signals (DBE3, DBE2, DBE1, DBE0) as 1,0, 0, 0 after passing through the 2-input 1-output multiplexer (9). Thus, the byte corresponding to bit 31 from bit 24 of the actual bus is selected.

The halfword access is operated in the same manner as described above. Therefore, according to the byte valid signal generating circuit of the present invention, while receiving the byte address designation signals A0 and A1, the output according to the byte size and the halfword size by the big endian / little endian bus structure designation signal BLB. By setting the value and again, if it is not a memory cycle request by ground (GND) and power (PWR), it outputs an output and a valid position different from the byte, halfword, and word size as the data byte valid signal (DBE). It can be seen that the use of the improved.

Claims (1)

In a memory access circuit of a 32-bit microprocessor, a big end when a byte is requested according to an input state of a big endian / little endian bus structure designation signal (BLB) while receiving byte address designation signals A0 and A1. Inverters I1 to I4, NOR gates N1 to N4 and four input one output multiplexers 1 to 4 for setting the byte size according to the bus structure / little endian bus structure, and the byte address designation signal ( An exclusive OR gate EX1 and an exclusive NOR gate EX2 for setting the byte size at the halfword request in accordance with A1) and the big-endian little-endian bus structure designation signal BLB, and the four-input one-output multiplexer (1) to (4), exclusive OR gate (EX1), exclusive NOR gate (EX2), ground (GND), and power supply (PWR) are connected to input terminals (D1), (D2), (D0), and (D3), respectively. Byte size memory access request signal WB and half word or more memory access request signal According to (WH), when not accessing the memory, the pixel is inputted with a 4-input one-output multiplexer (5-8) for outputting the byte, halfword, and word size, and the output of the four-input one-output multiplexer (5-8). A byte in a memory access circuit comprising a two input one output multiplexer (S) for outputting a data byte request signal (DBE) according to a big endian / little endian bus structure according to an instruction address selection signal (IPST). Effective signal generation circuit.