KR930006127B1 - Semiconductor memory having a compensation circuit for defect parts - Google Patents

Abstract

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Description

Semiconductor Memory with Fault Relief Circuit

1A to 8 illustrate the defect repair circuit examined by the present inventors and the problems found.

9 and 10 illustrate a first embodiment of the present invention.

11, 12 and 13 illustrate a second embodiment of the present invention.

14, 15 and 16 illustrate a third embodiment of the present invention.

17 illustrates a fourth embodiment of the present invention.

18 is a view for explaining a fifth embodiment of the present invention.

FIG. 19 shows a first embodiment of an address comparison circuit used in the present invention. FIG.

FIG. 20 shows a second embodiment of the address comparison circuit used in the present invention. FIG.

21 and 22 show a sixth embodiment of the present invention.

23, 24a, b and 25 show a seventh embodiment of the present invention.

26 and 27 show an eighth embodiment of the present invention.

28 and 29 show a ninth embodiment of the present invention.

30 shows a third embodiment of the address comparison circuit used in the present invention.

FIG. 31 shows a fourth embodiment of the address comparison circuit used in the present invention. FIG.

FIG. 32 shows a fifth embodiment of the address comparison circuit used in the present invention. FIG.

33 is a diagram showing an embodiment in which the present invention is applied to a one-chip microcomputer.

＊ Explanation of symbols on main parts of drawing

100 to 103: memory mat 200 to 203: sense amplifier and input / output line

300,301: X decoder 400: Y decoder

500: defect relief circuit 600: preliminary wand selection circuit

700: multiplexer 701: data input buffer

702: data output buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly to a technique for compensating by replacing defective memory cells with spare memory cells.

High integration of semiconductor memories is progressing rapidly in recent years, and mass production of megabits is also being mass-produced. However, there is a problem that efficiency decreases as the device becomes more compact and the chip area increases due to higher integration. As a countermeasure, there is a so-called defect repair technique which compensates by replacing a defective memory cell with a spare memory cell previously provided on a chip. This technique is very effective for improving the efficiency of semiconductor memories, as discussed, for example, in "IEEE, Journal of Solid Circuits, Vol. SC16, NO.5, P479-487 (October 1981)". Way.

In addition, there is a method proposed in Japanese Patent Laid-Open No. 60-130139. This allows the replacement of the normal line and the reserve line between the memory mats. However, this method has a problem in that the control of memory mat selection is complicated, especially when the mat division is large. This is because the memory mat to be selected must be changed depending on whether or not the access requested address is bad. In particular, in the case of DRAM, changing the memory mat to be selected is accompanied by a change in the sense amplifier to operate, leading to an increase in access time.

FIG. 1A shows an example of the configuration of a semiconductor memory to which the defect relief examined by the present inventors is applied. In the figure, reference numeral 10 denotes a memory array in which memory cells are arranged in a matrix, and includes regions 11 in which regular memory cells are arranged and regions 12 in which spare memory cells are arranged. In the region 11, N _W at the desired intersection of the N _W word lines W (i) (i = 0 to N _w- 1) and the N _B bit lines B (j) (j = 0 to N _B- 1). X N _B memory cells are arranged. In the region 12, L × N _B memory cells are arranged at intersections of L spare word lines SW (k) (k = 0 to L) and N _B bit lines. Note that the bit lines are two wirings in the case of the so-called folded bit line system, but are shown here as one line for simplicity. Denoted at 20 is a sense amplifier SA for amplifying a signal read from a memory cell and input / output line I / O for transmitting data (the common signal line when only one of inputs or outputs is used), and 30 is a row address. An X decoder for receiving one of the signals A _X (i) (i = 0 to n _w -1, n _w = log ₂ N _W ) and selecting one of the N _W word lines, 40 denotes a column address signal A _Y (j) (j = 0 ~ n -1 _B, n _B = _B logN) receives the Y decoder, 50, to select one of the n _B bits seonjung the defect redundancy circuit, 60 is a defect redundancy A preliminary word line selection circuit for selecting a preliminary word line by receiving the output of the circuit, 701 is a data input buffer, and 702 is a data output buffer.

Since this memory is provided with a defect repair circuit for word lines, when a normal word line is defective, it can be compensated by replacing it with one of the spare word lines. The defect relief circuit 50 and the spare word line selection circuit 60 are responsible for this. There are one address comparison circuit AC (k) (k = 1 to L-1), one for each of L (four in the drawing) and a total of L (four in the drawing). Each address comparison circuit stores the row address of the defective spare word line and compares whether it matches the address requested for access. The output XR (k) of the address comparison circuit AC (k) becomes a high level when the comparison result is "matched". The spare word line selection circuit 60 is composed of L spare word line drivers 650, as shown in FIG. The spare word line driver 650 is activated when XR (k) is at a high level, and the spare word line SW (k) is selected by the word line driving signal? _X. On the other hand, the output of the NOR gate 501 is at a low level, which causes the X decoder 30 to be disabled so that a regular word line to be originally selected cannot be selected. That is, the normal word line is replaced by the spare word line SW (k).

FIG. 2A shows another example of the configuration of the semiconductor memory to which the defect relief examined by the present inventors is applied. In the figure, reference numeral 10 denotes a memory array in which memory cells are arranged in a matrix, and includes regions 14 in which regular memory cells are arranged and regions 15 in which spare memory cells are arranged. Region 14 has N _W of word lines W (i) (i = N _W -1) N and _B of the intersection of the bit line B (j) (j = 0~N _B -1) N _W N × _B Memory cells are arranged. In the region 15, N _W x L memory cells are arranged at the intersection of L spare word lines SB (k) (k = 0 to L) and N _W word lines. 20 is input and output lines for transmitting a sense amplifier for amplifying a signal and data read out from the memory cell, 30 is a row address signal _X A (i) (i = 0~n _w -1, _w n = log ₂ N _W), the X decoder to select one of N of word _W seonjung receive, 40 column address signal _{a Y (j) (j =} 0~n B -1, n B = log 2 N _B) a Y decoder (50) for selecting one of the N _B bit lines are defect redundancy circuit receives, 63 spare bit line selection circuit for selecting a spare bit line receives the output of the defect redundancy circuit to be.

The present memory is provided with a defect repair circuit for the bit lines, and when the normal bit lines are defective, it can be compensated by replacing them with one of the spare bit lines. The defect relief circuit 50 and the spare bit line selection circuit 63 are responsible for this. There are one and a total of L address comparison circuits AC (k) (k = 0 to L-1) corresponding to the L reserved bit lines. Each address comparison circuit stores the column address of the defective spare bit line and compares whether or not it matches the address requested for access. The output YR (k) of the address comparison circuit AC (k) becomes high level when the comparison result is "matched". The preliminary bit line selection circuit 63 includes L drivers 680 as shown in FIG. 2B. The driver 680 is activated when YR (k) is at the level, and the spare bit line SB (k) is connected to the input / output line I / O via the MOS transistors 690 and 691 by the bit line selection signal ψ _Y. . On the other hand, the output of the NOR gate 501 is at a low level, which causes the Y decoder 40 to be disabled, so that the regular bit line to be originally selected is not selected. In other words, the normal bit line is replaced by the spare bit line SB (k).

The inventors of the present invention have found that the following problems occur as a result of high integration of the memory as a result of reviewing the joint rescue technique.

First, since the number of memory cells to be replaced at the same time by the defect remedy increases, the probability that the spare memory cell itself is defective is large. This is because the number of memory cells on one word line and bit line becomes large. For example, in the case of 256K bit memory (N _W = N _B = 512), 512 memory cells are replaced at the same time, but in the case of 16M bit memory (N _W = N _B = 4096), 4096 may be used. If the normal memory cell and the spare memory cell replaced are defective, the chip becomes defective. This is because the defect repair technique is based on the premise that there is no defect in the spare memory cell. Therefore, in the above technique, the effect of improving efficiency decreases as the memory is highly integrated.

This problem is exacerbated when the memory array needs to be partitioned as the memory becomes larger. In general, when the size of the memory becomes large, the number of memory cells connected to one word line and one bit line increases, so that the wiring length becomes long, and the signal propagation time increases due to the parasitic resistance of the wiring and the parasitic capacitance increases. Lowering the noise ratio is a problem. Therefore, it is widely practiced to divide the memory array into several memory mats to shorten the wiring length of one word line and bit line. However, if the above-described defect repair technique is applied to the mat and divided semiconductor memories, the following problems also occur.

FIG. 3 is a configuration example in the case where the memory array is divided into four memory mats (word lines divided into two, bit lines divided into two) in the semiconductor memory shown in FIG. 1A. In the drawing, reference numerals 100 to 103 denote memory mats, 200 to 203 denote sense amplifiers and input / output wires, 300 and 301 denote X decoders, 400 denotes Y decoders, and 610 Reference numeral 611 denotes a spare word line selection circuit, 700 a multiplexer, 701 a data input buffer, and 702 a data output buffer.

Each memory mat is composed of regions 110 and 113 in which regular memory cells are arranged and regions 120 to 123 in which spare memory cells are arranged. Regions 110, 111, 112, and 113 (corresponding to (11A), (11B), (11C), and (11D) in FIG. 1A, respectively), N _W / 2 word lines and N _{B respectively.} N _W x N _B / 4 memory cells are arranged at the intersections of the / 2 word lines and the N _B / 2 bit lines. L x N _B / 2 spare memory cells are arranged in regions 120 to 123 at the intersections of L spare word lines (L = 4 here) and N _B / 2 bit lines. For example, in the example described in the above document, N _W / 2 = 64, N _B / 2 = 128, and L = 4.

First, the word line selection method in this memory will be described. In this example, word lines are selected by two mats. For example, when the word line W (i, 0) in the memory mat 110 is selected, the corresponding word line W (i, 2) of the memory mat 112 is also selected at the same time. At this time, the memory mat 111 and the word line of 113 are not selected. In contrast, when the word lines of the memory mats 111 and 113 are selected, the word lines of the memory mats 110 and 112 are not selected. This is because the word lines W (i, 0) and W (i, 2) are originally divided into two word lines, which are physically two word lines, but can be considered logically as one word line. to be. The memory mats 110 and 112 are selected, or the 111 and 113 are selected as one of the row address signals (here, the highest A _X (n _W -1)). Further, the final memory cell selection is performed by the column address signal A _Y (j) (j = 0 to n _B- 1). At this time, whether the memory cell in the memory mat 110 or 111 is selected or the memory cell in the 112 or 113 is selected, the multiplexer 700 is one of the column address signals (where the highest A _Y ( n _W -1) to determine.

In this example, each address comparison circuit compares the row address signals except for the highest A _X (n _W −1). The output XR (k) of the address comparison circuit AC (k) is commonly supplied to the output XR (k) of each spare word line selection circuit AC (k). As shown in FIG. 4, the reserved word line selection circuit only reserves the reserved word lines of the memory mat selected by taking the logical product of XR (k) and the low address signal A _X (n _W -1) (or its auxiliary signal). To be driven.

In this memory, the replacement of the normal line and the reserve line is performed simultaneously with all the memory mats. This is explained using FIG. 5 shows an example of a word line replacement method. Here, the defective word lines W (0,0), W (2,0), W (1,1), and W (3,3) are reserved word lines SW (0,0) and SW (1, 0), SW (2,1) and SW (3,3) are substituted. However, other word lines are replaced at the same time. For example, replacing W (0,0) with SW (0,0), the corresponding word lines W (0,1), W (0,2), and W (0,3) of other memory mats At the same time, they are replaced by SW (0,1), SW (0,2), and SW (0,3), respectively.

The example shown in FIG. 3 has the following problems. The first problem is that the area for the preliminary word line is increased by dividing the mat as can be seen by comparing Figs. 1A and 3A. This is because L spare word lines are arranged for each of the divided mats. Since the region 12A in FIG. 1A corresponds to 120 and 121 in FIG. 3 and 12B corresponds to 122 and 123, respectively, the area for the spare word line is doubled. In general, when the word line is divided into M _W and the bit line is divided into M _B , the area for the spare word line is M _B times, and the area for the spare bit line (not shown in FIGS. 1A and 3) is M. _{W is} doubled. This results in an increase in chip area.

The second problem is that the number of memory cells replaced at the same time by the defect relief of the word line increases. This is because, as described above, the replacement of the normal line and the reserve line is executed simultaneously in all the memory mats. In general, when the word line is divided into M _W and the bit line is divided into M _B , the number of memory cells simultaneously replaced by the defect relief of the word line is M _B times, and the number of memory cells simultaneously replaced by the defect relief of the bit line is M _{W is} doubled. This results in a decrease in efficiency with the increase in the number of memory cells that are simultaneously replaced as described above. This problem is particularly serious in high density memory where M _W and M _B are large.

As a method of applying the defect repair to the mat-divided memory, the method shown in FIG. 6 is also considered. In this case, an address comparison circuit is provided for each spare line of every memory mat. Therefore, the number of address comparison circuits is 4L (here eight). Each address comparison circuit compares A _Y (n _B -1) at the top of the column address signal in addition to the row address signals A _X (0) to A _X (n _w -1).

FIG. 7 is a diagram showing an example of a word line replacement method in the memory of FIG. As can be seen by comparing this to FIG. 5, the method shown in FIG. 6 is superior to the method shown in FIG. The first is that the use efficiency of the reserve line is good, and the number L of reserve lines per memory mat can compensate for at least the same number of defects. This is because the probability that a large number of defects are concentrated in one memory mat is small. Second, the number of memory cells that are replaced at the same time is small.

However, the method shown in FIG. 6 has a problem in that the number of address comparison circuits increases. In general, when the word line is divided into M _W and the bit line is divided into M _B , the number of address comparison circuits is M _W M _B L. This results in an increase in chip area. In particular, high density memory where M _W and M _B are large becomes very serious.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory having a defect repair circuit having a large efficiency improvement effect in a small area.

Another object of the present invention is to provide a semiconductor memory having a defect repair circuit having a high use efficiency of redundant bits.

In order to achieve the object of the present invention, in the present invention, when the memory array is divided into M (M≥2) memory mats, the number m of word lines or bit lines that are simultaneously replaced by defect relief is a divisor of M less than M. Shall be.

In addition, not only " 0 " and " 1 " but also the money care value " X " The money care value is a value whose comparison value is "matched" even when the comparison partner (input address) is "0" or "1".

By making m smaller than M, the number of memory cells to be replaced at the same time in accordance with the defect relief is reduced. As a result, since the probability of a defect in the spare line itself is small, it is possible to provide a defect repair circuit having a large effect of improving efficiency even in a high density memory.

By allowing the address comparison circuit to store the money care value "X", it is possible to select whether or not to compare each bit of the address. As shown in Fig. 8, when " 0 " or " 1 " is stored in the address comparison circuit, the comparison result is " matched " or " unmatched " depending on the input address. That is, the corresponding bit of the input address is compared with the stored address. On the other hand, when "X" is stored in the address comparison circuit, the comparison result is "matched" regardless of the input address. That is, the corresponding bits of the input address are not compared. As a result, for example, the following defects can be repaired.

When all ratios (including row and column addresses) of the addresses are compared, the replacement of the normal memory cells with the spare memory cells is performed in units of 1 bit. If only the column addresses are to be compared, the bit line replacement is performed. If only the least significant bit of the column address is not compared, the replacement is performed in units of two bits. As described above, since it is very sensitive to various kinds of semiconductor memory defects such as bit defects, bit line defects, and bit pair defects, the effect of efficiency improvement can be expected as compared with the above-described technology.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Embodiments of the present invention will be described below with reference to the drawings.

The following description describes a case where a defect relief is introduced into a DRAM using a dynamic random access memory (DRAM), in particular, a one-transistor, one-capacitor-type memory cell. It is also applicable to other semiconductor memories such as read only memory), EEPROM (electrically rewritable read only memory). Moreover, although mainly describing a semiconductor memory using CMOS technology, the present invention is applicable to other technologies, for example, a semiconductor memory using unipolar MOS transistors, bipolar transistors or a combination thereof. Moreover, a combination of microcomputers using these semiconductor memories is particularly effective. It is also effective when the semiconductor memory and the microcomputer are provided on one chip.

Example 1

9 shows one embodiment of the present invention. In the drawing, reference numerals 100 to 103 denote memory mats, 200 to 203 denote sense amplifiers and input / output wires, 300 to 301 denote X decoders, 400 denotes Y decoders, and 500 denotes The defect repair circuit 600 is a preliminary word line selection circuit (the configuration is similar to that of FIG. 1B), 700 is a multiplexer, 701 is a data input buffer, and 702 is a data output buffer. Each memory mat is composed of regions 110 to 113 in which regular memory cells are arranged, and regions 120 to 123 in which spare memory cells are arranged. N _W / 2 word lines W (i, n) (i = 0 to N _W / 2-1, n = 0 to 3) and N _B / 2 bit lines B in the regions 110 to 113, respectively. is (j, n) (j = 0~N B / 2-1, n = 0~3) is N _W × N _B / 4 of memory cells arranged at the intersection of the. In the regions 120 to 123, L reserved word lines SW (k, n) (k = 0 to L-1, n = 0 to 3) and N _B / 2 At the intersection of the bit lines, L × N _B / 2 spare memory cells are arranged.

The array method of this embodiment is a folded bit line method, but the present invention can be similarly applied to an open bit line type memory. In the case of the folded bit line system, the bit line is composed of two wires, but for the sake of simplicity, one line is shown here. Details of the folded bit line method and the open bit line method are described, for example, in "IEE PROC., Vol. 130, Pt. I, No. 3, P127-135 (issued in June 1983)". have.

Hereinafter, the defect repair of the word line will be described according to the present embodiment. First, the word line selection method is described. In this embodiment, word lines are selected by two mats. For example, when the word line W (i, 0) in the memory mat 110 is selected, the corresponding word line W (i, 2) of the memory mat 112 is also selected at the same time. At this time, the word lines of the memory mats 111 and 113 are not selected. In contrast, when the word lines of the memory mats 111 and 113 are selected, the word lines of the memory mats 110 and 112 are not selected. This is because the word lines W (i, 0) and W (i, 2) originally divided one word line into two, which are physically two word lines, but can be considered logically as one word line. to be. The memory mats 110 and 112 are selected, or one of the thin row address signals for selecting the 111 and 113 (here, the highest A _X (n _W −1)) is determined. Further, the final memory cell selection is performed by the column address signals A _Y (j) (j = 0 to n _B- 1). At this time, one of the column address signals (here, the highest A _{Y in} the multiplexer 700 for selecting the memory cells in the memory mat 110 or 111 or the memory cells in the 112 or 113) is selected. (n _B -1)).

Next, a method of replacing a bad word line with a spare word line will be described. In the technique of FIG. 3, as shown in FIG. 5, four memory mats simultaneously replace regular word lines and spare lines. For example, if the word line W (0,0) of the memory mat 110 is bad, not only W (0,0) but also the corresponding word lines W (0,1), W (0,0) of another memory mat. 2), W (0, 3) is also replaced by a spare word line at the same time. However, in this embodiment, two memory mats selected at the same time are replaced at the same time. 10 shows an example of a method of replacing a word line in this embodiment. For example, when the word line W (0,0) of the memory mat 110 is defective, W (0,0) and W (0,2) are simultaneously replaced with a spare word line. However, the word lines of the memory mats 111 and 113 are not replaced.

In order to realize such a substitution method, the highest row address A _X (n _w −1) is compared in the address comparison circuit. The row address A _X (n _w −1) is an address that determines the memory mat to be selected as described above. In the technique of Fig. 3, since all the mats are replaced by the spare word lines at the same time, the row address A _X (n _w -1) is not compared in the address comparison circuit. On the other hand, in the present embodiment, the above substitution method is realized by comparing the row addresses A _x (n _w −1).

The first advantage of this embodiment is that the number of memory cells to be replaced at the same time by the above substitution method is reduced. In the technique of FIG. 3, N _B / 2 × 4 = 2N _B is substituted at the same time, but in the embodiment of FIG. 9, it is halved to N _B / 2 × 2 = 2N _B. As a result, the probability that the spare memory cell in which the regular memory cell is replaced is defective is less than that of the above-described technique, and the efficiency is improved. In this embodiment, since the number of divisions of the memory array is relatively small, the effect is not so remarkable, but the effect is very large in the highly integrated memory having a large number of divisions. This is because the probability that all spare memory cells are not defective is inversely proportional to the exponential function of the number of memory cells. Generally, in a memory in which word lines are divided into M _W and bit lines are divided into M _B , m m (m is a divisor of N _W N _B ) is replaced at the same time when a regular word line is replaced with a spare word line. The number of memory cells is M _B N _B in the all-mat co-substitution method, mN _B / M _W in the method according to the present invention, _and M / M _W M _B times the former (M _{W in the} embodiment of FIG. 9). = 2, M _B = 2, m = 2).

For example, in the case of N _W = N _B = 4096, M _W = 4, M = _B = 16, m = 8 in 16M bit memory, the number of memory cells replaced at the same time is 65536, In the method according to this embodiment, the number is 8192, which is 1/8, and the probability that the spare memory cell is defective is significantly smaller than before.

A second advantage of this embodiment is that the utilization efficiency of the spare memory cell is high. For example, consider the case of the word line W (i ₁ , 0) of the memory mat 110 and the word line W (i ₂ , 1) (i ≠ i ₂ ) of the memory mat 111. In the scheme shown in Fig. 3, two spare words lines per memory mat and eight reserved word lines are required to compensate for such defects. For example, W (i ₁ , O) to W (i ₁ , 3) are SW (0,0) to SW (0,3), and W (i ₂ , 0) to W (i ₂ , 3) May be replaced with SW (1,0) to SW (1,3), respectively. This can be compensated for by four spare word lines, one per mat in the present embodiment. For example, W (i ₁ , 0) and W (i ₁ , 2) are SW (0,0) and SW (0,2), and W (i ₂ , 1) and W (i ₂ , 3) May be replaced with SW (0,1) and SW (0,3), respectively. Therefore, the spare word lines SW (1,0) to SW (1,3) can be allocated to compensation of other defects, so that an improvement in efficiency can be expected.

Another advantage of this embodiment is that the degree of freedom in selecting the number L of spare word lines per memory mat and the number R of address comparison circuits is large. In the scheme shown in Fig. 3, since the regular word line is replaced with the spare word line at the same time as all the mats, it must be L = R. For example, in Fig. 3, L = R = 4. On the other hand, in the method according to the present invention, L and R can be selected relatively freely, so that a highly efficient defect repair circuit can be made in a small area. The relationship between L and R will be described next.

In general, when the normal line of m mat is replaced by the reserve line at the same time,

This holds true. The inequality sign on the left indicates that it is not meaningful to provide more reserved numbers than the number of address comparison circuits in each memory mat. The inequality sign on the right means: Each memory mat has L spare lines, and since the number of mats is M _W M _B , there are physically a total of LM _W M _B spare lines. However, since m is replaced at the same time, the logical reserves are LM _W M _B / m. The inequality sign on the right side of Equation (1) indicates that it is meaningless even if the number of address comparison circuits is larger than the logical reserved number. In the scheme of FIG. 3, since m = M _W M _B , L = R. On the other hand, in the system according to the present invention, L and R can be freely selected within a range satisfying Expression (1).

In terms of chip area, it is desirable to increase R rather than L. This is because the area increase by providing one address comparison circuit is usually smaller than the area increase by providing one spare line in all memory mats. In the conventional method, only R was not able to increase due to the relationship of L = R, but it is possible according to the present invention. Therefore, by making L relatively small and R relatively large, a highly efficient defect repair circuit can be produced in a small area. That is, the feature of the present invention is the relationship except for the equal sign on the left in (1),

You can do it. For example, in the embodiment of Fig. 9, M _W = M _B = 2 and m = 2, so that Equation (2) is L < R < SL (actually L = 2 and R = 4).

Moreover, when R is made larger than L, a case where compensation cannot be made irrespective of the number of defect lines being R or less. For example, a defect line is concentrated in one memory mat, and the number is more than L and less than R. In this case, the number of address comparison circuits is sufficient, but compensation is impossible because the number of physical spare lines of the defective memory mat is insufficient. However, since the probability of concentrating a large number of defects on one memory mat is small, if L is set to, for example, two or more, such problems rarely occur.

This embodiment is applicable to the memory of the address multiplex method and to the memory which is not the address multiplex method.

Example 2

As can be seen from the above description, the smaller the number m of word lines that are simultaneously replaced by the defect remedy, the more preferable. 11 is an example in which m = 1. The difference from the embodiment of Fig. 9 lies in the method of selecting word lines and the method of replacing defective word lines. In the case of Fig. 9, the word lines are simultaneously selected by two mats, and the replacement with the spare word lines is also performed simultaneously by two mats. In this embodiment, the selectivity of the word lines and the substitution with the spare word lines are also performed one by one.

To do this, the column address signal A _Y (n _B-1 ) is used. A _Y (n _B-1 ) is an address that distinguishes the memory mats 110, 112, 111, and 113 as described above. First, not only the row address but also A _Y (n _B-1 ) is input to the X decoder so that only one of the four memory mats is selected. In the address comparison circuit, not only the row address but also A _Y (n _B-1 ) is compared so that replacement of the regular word line and the spare word line is performed one by one. In addition, the preliminary word line selection circuits 610 to 613 are changed as shown in FIG. Here, only the reserved word lines of the selected memory mat are driven by taking the logical product of XR (k) and the column address signal A _Y (n _B-1 ) (or its auxiliary signal).

Thus, the use of the column address for the defect relief of the word line is a feature of this embodiment. In the above-described defect repair technique, only the row address is used for the defect repair of the word line, and only the column address is used for the defect repair of the bit line. However, in the mat-divided memory, the following effects are obtained by using the column address for the defect relief of the word line or the row address for the defect relief of the bit line as in the present embodiment.

13 shows an example of the word line replacement method in this embodiment. Since the number m of word lines to be replaced at the same time is m = 1, the number of memory cells to be replaced at the same time is less than 1/2 of the embodiment of FIG. As a result, the probability of defects in the preliminary memory cells becomes smaller, and the effect of improving the efficiency is further increased.

Further, the use of spare memory cells becomes higher than in the embodiment of FIG. 9 by reducing the number of word lines to be replaced at the same time. For example, when the word lines W (i ₁ , 0) and W (i ₂ , 1) (i ₁ ≠ i ₂ ) are defective, four spare word lines are required for compensation in the embodiment of FIG. In contrast, in the present embodiment, two spare word lines can be compensated.

In the present embodiment, since the number of word lines m replaced at the same time is smaller than that in FIG. 9, the degree of freedom in selecting the number of address comparison circuits R is larger than that in FIG. Therefore, it is possible to make a more efficient defect repair circuit according to the occurrence condition of the defect. This is clear when comparing this embodiment with the technique of FIG. In the case of the technique of Fig. 6, since an address comparison circuit is provided corresponding to all spare word lines of all memory mats, R = LM _W M _B, i.e., the equal sign on the right side of equation (1) is established. However, in the present invention, the equal sign on the right side of the formula (1) may not necessarily hold. This means that if the number of defects is not so large, R can be reduced than in the case of the technique of FIG. Therefore, the increase of the chip area by the address comparison circuit can be suppressed. In the present embodiment, since m = 1 and L = 2,

L = 2≤R≤8 = LM _W M _B / m

And is actually R = 4.

(Example 3)

14 shows a third embodiment of the present invention. In this embodiment, the address comparison circuit and the spare word line selection circuit are not directly connected through the switch circuit 510 and the OR gates 505 and 506. However, according to this, the preliminary word line selection circuits 620 to 623 are changed as shown in FIG. Here, the reserved word lines of the memory mat selected by taking the logical product of XL (k) and the address signals A _X (n _W-1 ) and A _Y (n _B-1 ) (or its auxiliary signal) for selecting the memory mat. Only let it run. Features of this embodiment are as follows.

The first feature is that the number of wirings from the defect repair circuit 500 to the preliminary word line selection circuits 620 to 623 is reduced. The number of wirings is R in the embodiment of Fig. 11 and L in this embodiment. As described above, in the present invention, since L < R in general, the number of wirings is smaller in this embodiment.

The second feature is that flexibility in use of the address comparison circuit is large because the correspondence relationship between the address comparison circuit and the spare line is flexibly changed. In the above embodiments, the correspondence relationship between the address comparison circuit and the spare line is fixed. For example, in the technique of FIG. 3, AC (k) is dedicated to SW (k, 0) to SW (k, 3) (k = 0 3). In the technique of FIG. 6, AC (k, 1) is dedicated to SW (k, 1) (k = 0,1,1 = 0-3). In the embodiment of Fig. 11, AC (2k) is dedicated to SW (k, 0), SW (k, 2), and AC (2k + 1) is dedicated to SW (k, 1) and SW (k, 3) (k = 0,1).

However, there is no such restriction in this embodiment, and one address comparison circuit can correspond to any spare word line by switching between the address stored in the address comparison circuit and the switch circuit 510. Among the addresses stored in the address comparison circuit, one memory mat is determined by two bits of A _X (n _w-1 ) and A _Y (n _B-1 ), and one in the memory mat is determined by the switch 510. Preliminary word lines are determined. As a result, the probability of success of the joint rescue is increased. For example, consider a case where there are two bad word lines in each of the memory mats 110 and 112. Such defects cannot be compensated in the embodiment of FIG. 11, but can be compensated in the present embodiment.

The third feature is that the correspondence relationship between the address comparison circuit and the spare line can be flexibly changed as described above, and therefore, it is resistant to the failure of the address comparison circuit. For example, when the address comparison circuit AC (0) is used to use the spare word line SW (0,0), it is said to have failed. In this case, for example, AC 1 may be used.

In addition to the above three points, the features of the above-described embodiment of FIG. 11 are applied to this embodiment as it is.

An example of the switch circuit 510 used in this embodiment is shown in FIG. 16, in which 511 is a fuse cut by a laser, and 512, 518, and 520 are N-null MOS transistors. , 517 and 519 are P-channel MOS transistors, 513 are fuses, 512, 518 and 520 are N-channel MOS transistors, and 517 and 519 are P-channel MOS transistors. Reference numeral 513 denotes an inverter, and 514 and 515 denote NAND gates. When the fuse is not blown, the node 532 is at low level, 533 is at high level, and terminals X and Z are conductive. When the fuse is blown, the node 532 becomes high level and 533 becomes low level, so that the terminals y and z conduct.

This embodiment is an improvement of the embodiment of FIG. 11, but the same improvement is also possible to the embodiment of FIG.

(Example 4)

17 shows a fourth embodiment of the present invention. In this embodiment, two logical sums of two (typically R / L) of two (typically R / L) are used instead of wiring the outputs XR (0) to XR (3) of four (generally R) address comparison circuits. The signals XL (0) and XL (1) (typically L) are wired. However, according to this, the spare word line selection circuits 620 to 623 are changed as shown in FIG. 15 described above. Here, only the reserved word lines of the memory mat selected by taking a logical product of XL (k) and the address signals A _X (n _W-1 ) and A _Y (n _B-1 ) (or its auxiliary) for selecting the memory mat. To be driven. Features of this embodiment are as follows.

First, the features of the above-described embodiment of FIG. 14 can be applied to this embodiment as it is. That is, firstly, the number of wirings of the spare word line selection circuit in the defect repair circuit is small. Second, since the correspondence relationship between the address comparison circuit and the spare line can be flexibly changed, the flexibility of using the address comparison circuit is large. Third, it is resistant to the failure of the address comparison circuit. In addition to this, this embodiment has the following features. First, the circuit configuration is simple as compared with the embodiment of FIG. Next, even if the fuse of the switch circuit is not blown, the correspondence relationship between the address comparison circuit and the spare line can be changed by simply changing the address stored in the address comparison circuit. Among the addresses stored in the address comparison circuit, one memory mat is determined by two bits of A _X (n _w-1 ) and A _Y (n _B-1 ).

In the present embodiment, as can be seen from the above description, R is preferably a multiple of L.

This embodiment is an improvement of the embodiment of FIG. 11, but the same improvement is also possible to the embodiment of FIG.

11, 14, and 17 are superior to the method of FIG. 9 (m = 2) in that m = 1 as described above, but these methods are conventional address multiplex methods. It cannot be applied to defect repair of word lines of DRAM as it is.

The first reason is that in DRAM, since the memory cells need to be regenerated, the number of word lines to be simultaneously selected cannot be arbitrarily set. The number of memory cells that are simultaneously playing when claim 9 degrees, when N _B with respect to individual claim 11 degrees, 14 degrees, 17 degrees is N _B / 2 atoms. Therefore, in order to apply these methods to DRAM, it is necessary to change the state of the number of the regeneration cycles. The second reason is that the column address signal cannot be used since the column address signal has not yet been input at the time of word line selection for the address multiplex method. However, in the case where there is no problem as described above, for example, in the case of SRAM or when there is no restriction on the number of reproduction cycles in a DRAM other than the address multiplex method, these methods can be applied. In ordinary DRAMs, these methods can be applied to the defect relief of bit lines. This is because the number of bit lines selected at the same time is not affected by the number of reproduction cycles, and the row address signal is already input at the time of bit line selection.

Example 5

For the above reason, in the case of defect relief of the word line of the DRAM, it is preferable to simultaneously replace the memory cells to be reproduced at the same time as in the embodiment of FIG. However, even in the case of defect relief of the word line of DRAM, m = 1 can be set in the case of FIG. This divides the memory array into four, but divides the word lines into four bit lines without dividing them. The defect repair method is the same as that of the embodiment of FIG. In this case, the number of memory cells that are simultaneously played back because a ninth help similarly numbered, N _B, the address signal to determine the memory mat is selected both the row address signal.

In this embodiment, only one Y decoder 40 is provided at the end, and the output YS (j) is supplied to each memory mat by wiring indicated by a dashed line in the figure. This is called a multi-bit bit line, and the area is reduced by using the Y decoder in several memory mats. In addition, the sense amplifier and the input / output line are shared by two memory mats. That is, 240 is shared by 130 and 131, and 241 is shared by 132 and 133, respectively. This is called a shared sense and is effective for reducing the area of the sense amplifier. For multi-bit bit lines and shared senses, see, for example, "ISSCC Digest of Teachnical Papers, P. 282-283 (February 1984)" or U.S.P.No. 4,675,845.

All of the above Examples 1 to 5 are examples of applying the present invention to the defect relief of word lines. However, the present invention can also be applied to defect relief of bit lines.

Example 1 of the Address Comparison Circuit

Next, an address comparison circuit used in the present invention will be described. 19 is an example of an address comparison circuit used for the semiconductor memory of FIG. In the figure, 801 is an N-channel MOS transistor, 802 and 803 are P-channel MOS transistors, and 804 is an inverter. Numeral 810 denotes a bit comparison circuit that stores one bit of a bad address and compares it with one bit of an address signal, 811 denotes a fuse cut by a laser, and 812 and 821 to 824 denote N. Channel MOS transistors 817 to 820 are P-channel MOS transistors, 813 are inverters, and 814 and 815 are NAND gates. The operation of this circuit will be described below.

First, the transistor 802 is turned on with the precharge signal XDP at low level, and the node 805 is set at high level. At this time, the output XR is at a low level. Next, an address signal A _X (i) (i = 0 to n _w-1 ) is applied. Each bit comparison circuit 810 compares the 1 bit of the bad address stored in the circuit with A _X (i), and if it matches, sets the output C (i) to a high level and to a low level if there is a mismatch. When the comparison results of all the bit comparison circuits coincide, the transistors 801 are all in a conductive state. At this time, the node 805 is discharged to a low level, and the output XR becomes a high level. That is, it is determined that the applied address coincides with the bad address. If any one bit of the address does not match, the node 805 is not discharged, and thus the output XR remains low level. In addition, the transistor 803 is a transistor having a relatively small conductance, and is for latching the potential of the node 805. When the node 805 is not discharged, the output XR is low level, so the transistor 803 is in a conductive state. As a result, the potential of the node 805 is maintained at a high level.

Next, the bit comparison circuit 810 will be described in detail. This circuit stores one bit of the bad address depending on whether or not the fuse 811 is blown. Here, "0" corresponds to the state where the fuse is not cut and "1" corresponds to the state where the fuse is cut. When the fuse is not blown, the node 830 becomes high level and 831 becomes low level. The outputs of the latches, which are two cross-coupled NAND gates 814 and 815, are at node 832 at low level and at 833 at high level.

가 고레벨일 때에 출력 C(i)가 고레벨로 된다. 퓨즈가 절단되어 있을 때는 각 노드의 전위가 상기와는 반대로 되고, 어드레스 신호 A_X(i)="1"일때에 출력 C(i)가 고레벨로 된다. 또한, 비트 비교회로의 하나로는 어드레스 신호 A_X(i),

대신에 각각 전원 Vcc, 타이밍 신호

(어드레스 신호와 같은 타이밍으로 고레벨에서 저레벨로 변화하는 신호)가 입력되어 있다. 소위 인에이블 회로이며, 결함구제를 위하여 이 어드레스 비교회로를 사용하는가 아닌가를 결정하기 위한 것이다. 사용하는 경우는 퓨즈를 절단한다. 퓨즈가 절단되어 있지 않을 때는 에이블 회로의 출력 E는 항상 저레벨이므로 어드레스 비교회로의 출력은 XR은 항상 저레벨이다.Therefore, when the address signal A _X (i) = " 0 ", that is, the true signal A _X (i) is low level, the auxiliary signal

Is at a high level, the output C (i) is at a high level. When the fuse is blown, the potential of each node is reversed to the above, and when the address signal A _X (i) = " 1 ", the output C (i) becomes a high level. In addition, one of the bit comparison circuits includes an address signal A _X (i),

Instead of power Vcc and timing signals respectively

(A signal that changes from high level to low level at the same timing as the address signal) is input. It is a so-called enable circuit, and is used to determine whether or not to use this address comparison circuit for defect repair. If used, cut the fuse. When the fuse is not blown, the output E of the enable circuit is always at the low level, so the output of the address comparison circuit is always at the low level.

As described above, in the embodiments of Figs. 11, 14, and 17, the column address A _Y (n _B-1 ) is also compared. This can be realized by adding the bit comparison circuit 810 and the MOS transistor 801 one by one.

The device for storing the bad address is not limited to the fuse cut by the laser shown here. An electrically cut fuse or a nonvolatile memory such as an EPROM may be used.

Example 2 of the Address Comparison Circuit

20 shows another embodiment of the address comparison circuit. This embodiment is suitable for application to the semiconductor memory of FIG. 17 or FIG. The difference from the previous embodiment is that the circuit combining the bit comparison circuit 810 and the N-channel MOS transistor 801 is provided with two sets 850 and 851. The defective addresses are stored in the circuits 850 and 851, respectively. The operation of the embodiment will be described below.

First, the precharge signal XDP is set at low level, and the node 805 is set at high level. Next, the address signal A _X (i) (i = 0 to n _w-1 ) is applied. At this time, the comparison of bad addresses is performed in the circuits 850 and 851, respectively. When the applied address coincides with either one of the bad addresses stored in the circuits 850 and 851, the node 805 is discharged, and the output XL is at a high level.

As can be seen from the above description, the circuit of this embodiment is equivalent to a circuit in which the OR gates 502 or 503 are added to the two address comparison circuits in the defect relief circuits of Figs. Therefore, using this circuit, the OR gate of FIG. 17 or 18 is unnecessary. Further, since the discharge time of the node 805 is the same as in the previous embodiment, the delay caused by the addition of the OR gate can be eliminated.

[Utility of money care]

The defect relief of the bit line of the memory having the configuration as shown in FIG. 18, and a defect that may occur over several memory mats may occur. This is because the Y decoder and the sense amplifier are shared by several memory mats. However, this problem can be solved by storing not only "0" and "1" but also the money care value "X" in the address comparison circuit as described below. Hereinafter, an embodiment using the don care value will be described.

Example 6

FIG. 21 shows a sixth embodiment of the present invention. In the figure, reference numeral 10 denotes a memory array, 20 denotes a sense amplifier and an input / output line, 30 denotes an X decoder, 40 denotes a Y decoder, 500 denotes a defect repair circuit, and 630 denotes a reserved bit line. The circuit (the configuration is similar to that in Fig. 33), 701 denotes a data input buffer, and 702 denotes a data output buffer. The memory array 10 is composed of an area 14 in which regular memory cells are arranged and an area 15 in which spare memory cells are arranged. Region 14 is _W N × N _W at the intersection of the word lines W (i) (1 = 0~N W-1) and _B N of the bit line B (j) (j = 0~N B-1) N _B memory cells M (i, j) are disposed. Region 15 has one of the word lines _W N L (here L = 2) pre-bit lines SB (k) (k = 0~L -1) _× L _W N junction of spare memory cells are arranged in the have. The array method of this embodiment is a folded bit line method, but the present invention can be similarly applied to an open bit line type memory.

Hereinafter, the characteristic of the defect repair in a present Example is demonstrated. The features of the defect repair circuit of this embodiment are that the row address signals A _X (0) to A _X (n _w-1 ) as well as the signal at the column address are input to each address comparison circuit AC (k) and the address comparison circuit. You can remember the money care value "X". This makes it possible to avoid comparing row addresses in the address comparison circuit. In the case of the technique of FIG. 2A, only the column address is compared in the address comparison circuit. This is because regular memory cells and spare memory cells are replaced in units of bit lines. In the present embodiment, if the row addresses are not compared, replacement in units of bit lines can be realized as in the prior art. On the other hand, when the row addresses are compared, the regular memory cells and the spare memory cells can be replaced in units of 1 bit.

This will be explained using FIG. Fig. 22 is a table showing an example of the replacement method of regular memory cells and EBI memory cells possible in the defect repair circuit of this embodiment. In the figure, a mark indicates that the addresses are compared (to store "0" or "1"), and the x mark indicates not to compare the addresses (to store "X"). As shown in the first column of the table, when both row addresses and column addresses are compared, replacement of the normal memory cell and the spare memory cell is performed in units of 1 bit. If the row addresses are not compared as in the third column, replacement is performed in units of bit lines as in the prior art. Also, as in the second column, if only the least significant bit of the row address is not compared, the replacement is performed in units of two bits.

In this way, the use of the row address for the defect relief of the bit line is another feature of this embodiment. In the conventional defect repair technique, only row addresses are used for defect repair of word lines, and only column addresses are used for defect repair of bit lines. However, as in the present embodiment, the above-described various substitution methods can be realized by using a row address for defect repair of a bit line or using a column address for defect relief of a word line.

Advantageous Effects of the Invention The advantage of the present invention can be extremely sensitive to various defects of the semiconductor memory according to the above various substitution methods. In general, a failure of a semiconductor memory may include one bit failure (for example, caused by a pinhole of a memory cell capacitor), a bit pair defect (for example, due to a contact failure), a bit line defect (for example, disconnection of a bit line). It is caused by). In the technique of FIG. 2A, even one bit of defect is replaced with a spare bit line in the entire bit line including the defective memory cell. On the other hand, in this embodiment, only one bad memory cell can be replaced with a spare memory cell in the case of a bad 1 bit, and only 2 bad memory cells in the case of a bad bit pair. Of course, in the case of a bit line failure, replacement in a bit line unit is also possible. By substituting only the minimum required memory cells with spare memory cells in this way, the probability that a spare memory cell has replaced the normal memory cell with a defect becomes smaller than before, thereby improving efficiency. The probability that all spare memory cells are not bad is inversely proportional to the exponential function of the number of memory cells.

In addition, since the minimum necessary spare memory cell is used to compensate for the defect, the use efficiency of the spare memory cell is high. For example, consider the case where the normal memory cells M (i ₁ , j ₁ ) and M (i ₂ , j ₂ ) (i ₁ ≠ i ₂ , j ₁ ≠ j ₂ ) are defective.

In this case, two spare bit lines are required for compensation in the scheme of FIG. 2A. However, in the present embodiment, for example, by storing bad addresses (i ₁ , j ₁ ) in the address comparison circuit AC (0) and storing (i ₂ , j ₂ ) in the address comparison circuit AC 1, respectively. Only one reserved bit line SB (0) can compensate. Therefore, since the spare bit line SB 1 can be made up for compensating for other defects, the improvement in efficiency is expected.

Next, the defect repair circuit 500 will be described in detail. The defect repair circuit of this embodiment includes R OR (here R = 4) address comparison circuits AC (k) (k = 0 to R-1) and R / L OR (here R / L = 2) OR gates 502, 503, and the NOR gate 504. L signals YL (0) and YL (1), which are logical sums of the outputs YR (0) to YR (3) of the R address comparison circuits, are wired to the reserved bit line selection circuit 630 to reserve bits. Used to select lines. The NOR gate 504 is for disabling the Y decoder 40 when any one of YR (0) to YR (3) becomes high level.

A feature of the present invention is that the degree of freedom in selecting the number L of spare bit lines and the number R of address comparison circuits is large. In the conventional method, L = R must be replaced since the bit line is replaced in units. For example, in Fig. 2a, L = R = 4. On the other hand, in the method according to the present invention, since L and R can be selected relatively freely, an efficient defect repair circuit can be made in a small area. The relationship between L and R will be described next.

In general, assuming that b is the number of regular memory cells replaced with spare memory cells at one time,

This holds true. The inequality sign on the left indicates that it has no meaning even if more spare lines are provided than the number of address comparison circuits.

The inequality sign on the right means: There are LN _W spare memory cells, but since the double b type is substituted at the same time, the degree of freedom of substitution is LN _W / b. Therefore, there is no meaning even if the number of address comparison circuits is larger than this. In the method of substituting bit line units, since b = N _W , L = R must be used. With respect to it in the manner of this embodiment is b may be freely selected from the range of 1≤b≤N _W, L, the degree of freedom of selection of the R becomes large.

In terms of chip area, it is preferable to increase R rather than L. This is because the area increase by providing one address comparison circuit is usually smaller than the area increase by providing one spare line in all memory mats. In the scheme of FIG. 2A, only R cannot be increased in consideration of the relationship L = R, but it is possible according to the present invention. Therefore, by making L relatively small and R relatively large, an efficient defect repair circuit can be made in a small area.

That is, the feature of the present invention is the relationship except for the left equal sign in the formula (3),

You can do it. For example, in the embodiment of Fig. 21, L = 2 and R = 4. As can be seen from this example, R is preferably a multiple of L.

Example 7

23 shows a seventh embodiment of the present invention. The difference from the previous embodiment lies in the wiring method of the output of the address comparison circuit. In the present embodiment, the signal YL, which is the logical sum of YR (0) to YR (3), is wired to the reserved bit line selection circuit 640. As a result, the configuration of the preliminary bit line selection circuit 640 is changed as shown in FIG. 24A or 24B. This is to prevent multiple selection of spare bit lines. In FIG. 24A, by taking the logical product of the address signal A _Y (0) (or its auxiliary signal) for selecting YL and the bit line, in FIG. 24B, the bit line selection circuit ψ _Y is free with respect to A _Y (0). By creating the decoded signals ψ _Y0 and ψ _Y1 , only one spare bit line is selected.

The characteristic of the present embodiment is that the substitution by two bit lines is possible. This will be explained using FIG. The first column, the second column, and the fifth column in the table of FIG. 25 are cases of bit defects, bit pair defects, and non-ray defects, respectively, as in FIG. The third column is a bad bit pair, but two adjacent bits on the same word line are bad (the second column is adjacent two bits on the same bit line).

Such defects are caused by, for example, short circuits between memory cell capacitors. The fourth column is a case where 2x2 bits are bad. Such defects are caused by poor contact, for example in the case of SRAM. The sixth column is a case where two adjacent bit lines are defective. Such defects are caused by short circuits between the bit lines, for example. By using this embodiment, various defects as described above can be easily compensated for.

Another feature of this embodiment is that the number of wirings between the defect repair circuit 500 and the preliminary bit line selection circuit 640 is small.

Example 8

FIG. 26 shows an eighth embodiment of the present invention. The difference from the previous two embodiments is that the array is divided into a plurality of memory mats 130 to 133 in the bit line direction (four here). Each memory mat has regions 140 to 143 in which regular memory cells are arranged, and regions 150 to 153 in which spare memory cells are arranged. N _W / 4 word lines W (i, n) (i = 0 to N _W / 4-1, n = 0 to 3) and N _B bit lines B (j) in the regions 140 to 143, respectively. _{, n) (j = 0~N B} -1, n = 0 to 3 are) crossing the N × N _{W B} / 4 memory cells are arranged in a. Regions 150 through 153 each have N _W / 4 word lines W (i, n) (i = 0 to NW / 4-1, n = 0 to 3) and L (here L = 2). N _W x L / 4 spare memory cells are arranged at the intersections of the spare bit lines B (k, n) (k = 0 to L-1, n = 0 to 3). Sense amplifiers and input / output lines 230 and 233 are provided corresponding to each memory mat. However, only one Y decoder 40 is provided at the end. The output YS (j) of the Y decoder is supplied to each memory mat in accordance with the wiring indicated by a dashed line in the figure. The same applies to the output SYS (k) of the reserved bit line selection circuit 630. This method is called bit line division, and the Y decoder is shared by several memory mats to reduce the area.

The present invention is particularly effective when the circuits (in this case, Y decoders and their output wirings) are shared by several memory mats as in this embodiment. This is because, if a circuit is in common use, a defect may occur over several memory mats. However, the present invention can easily compensate for such a defect. This is explained using FIG. The first column and the second column of the table are the cases of bit defects and bit pair defects, respectively, as in FIG. The third column is a case of bit line failure. In this case, however, since the memory array is divided into four, the address signal for selecting the memory mat (here, the upper two bits of the low address, A _X (n _W-1 ) and A _X (n _W-2 ) are compared. This replaces only the bit lines of one memory mat with the spare bit lines, and the fourth column in the table is a case where the Y decoder is defective, in which case A _X (n _W-1 ) and A _X (n _W-2). ) Are not compared, whereby the bit lines at the corresponding positions of the four memory mats are replaced by spare bit lines at the same time.

Example 9

28 shows a ninth embodiment of the present invention. The difference from the embodiment of FIG. 26 is that the sense amplifier and the input / output lines are shared by two memory mats. That is, 240 is shared by 130 and 131, and 241 is shared by 132 and 133, respectively. This is called a shared sense and is effective for reducing the area of the sense amplifier.

In the present embodiment, if the sense lamp is defective, the bit lines corresponding to the left and right mats are defective at the same time. However, the present invention can easily compensate for such a defect. This is explained using FIG. The first column, the second column, the third column, and the fifth column in the table are the cases of bit defects, bit pair defects, bit line defects, and Y decoder defects, respectively. The fourth column is a case where the sense amplifier is bad. In this case, only the address signals (here, A _X (n _W-1 )) for selecting whether to select the memory mats 130 and 131 or 132 and 133 among the row addresses are compared. . As a result, the bit lines at positions corresponding to the left and right memory mats of the sense amplifiers are replaced with spare bit lines.

All of Examples 6 to 9 described above were examples of applying the present invention to defect repair of bit lines. However, the defect relief using the money care value is also applicable to the defect relief of the word line.

Example 3 of the Address Comparison Circuit

Next, an address comparison circuit for use in Examples 6 to 9 will be described. The address comparison circuit used here is characterized in that, as described above, three values of " 0 ", " 1 " and " X " 30 shows a third embodiment of the address comparison circuit. In the figure, reference numeral 800 is an AND gate. Reference numeral 810 denotes a bit comparison circuit that stores one bit of a bad address and compares it with one bit of an address signal. Reference numerals 861 to 863 denote laser fuses, 864 and 867 are inverters, and 865 and 866 are NAND gates. Reference numeral 809 is an enable circuit and is used to determine whether to use the corresponding address comparison circuit for the defect repair circuit. Reference numeral 811 denotes a fuse cut by a laser, 812 denotes an N-channel MOS transistor, 813 denotes 816, an inverter, and 814 denotes a NAND gate. The operation of this circuit will be described below.

First, the enable circuit will be described. When using the address comparison circuit for defect repair, the fuse 811 in the enable circuit is first blown. As a result, the node 830 becomes low level, 831 becomes high level, 832 becomes high level, and 833 becomes low level. Therefore, the enable signal E becomes high level. When the fuse 811 is not blown, the potential of each node is reversed from the above, and the enable signal E is at a low level.

(또는

가 고레벨일 때에 출력 C_X(i)(또는 C_Y(j))가 고레벨로 된다. "1"을 기억시킬 때는 퓨즈(861) 및 (863)을 절단한다. 이것에 의해 어드레스가 "1"일 때, 즉 참신호 A_X(i)(또는 A_Y(j))가 고레벨, 보조신호

(또는

)가 저레벨일때에 출력 C_X(i)(또는 C_Y(j))가 고레벨로 된다. "X"를 기억시킬 때는 퓨즈(862)및 (863)을 절단한다. 이때는 어드레스의 여하에 관계없이 출력 C_X(i)(또는 C_Y(j))가 고레벨로 된다. 모든 비트 비교회로의 비교결과가 일치할 때, AND게이트(800)의 출력 YR이 고레벨로 된다. 즉, 인가된 어드레스가 불량어드레스와 일치하였다고 판정된다. 어드레스중, 1비트라도 일치하지 않으면, YR은 저레벨로 된다. 또한, 상기는 인에이블 신호 E가 고레벨인 경우이다. 인에이블 신호 E가 저레벨일 때, 모든 비트 비교회로의 출력 C_X(i)(또는 C_Y(j))는 저레벨이며, 따라서 YR도 저레벨이다.Next, the bit comparison circuit will be described. The bit comparison circuit 810 compares the stored value with the address A _X (i) (or A _e (j)) according to the disconnection state of the fuse, and if it matches, output C _X (i) (or C _Y (j). )) Is high level, and if there is a mismatch, C _X (i) is set low. The method of cutting the fuse is as follows. When storing "0", the fuses 861 and 862 are blown. As a result, when the address is "0", that is, the true signal A _X (i) (or A _Y (i)) is low level, the auxiliary signal.

(or

Is at a high level, the output C _X (i) (or C _Y (j)) is at a high level. When storing "1", the fuses 861 and 863 are cut off. As a result, when the address is "1", that is, the true signal A _X (i) (or A _Y (j)) is high level, the auxiliary signal

(or

) Is at a low level, the output C _X (i) (or C _Y (j)) is at a high level. When storing "X", the fuses 862 and 863 are blown. At this time, the output C _X (i) (or C _Y (j)) becomes a high level regardless of the address. When the comparison results of all the bit comparison circuits coincide, the output YR of the AND gate 800 becomes high level. That is, it is determined that the applied address coincides with the bad address. If even one bit of the address does not match, YR is at a low level. The above is also the case where the enable signal E is at a high level. When the enable signal E is at low level, the output C _X (i) (or C _Y (j)) of all the bit comparison circuits is at low level, and thus YR is also at low level.

The characteristic of this embodiment is that the circuit size is small, so that the occupied area can be reduced.

Further, the device for storing the defective address is not limited to the fuse cut by the laser shown here. An electrically cut fuse or a nonvolatile memory such as an EPROM may be used.

[Example 4 of the address comparison circuit]

FIG. 31 shows a fourth embodiment of the address comparison circuit. The difference from the previous embodiment is the configuration of the bit comparison circuit 810. 871, 881, 882 are laser cut fuses, 872 are N-channel MOS transistors, 873, 887 are inverters, 874, 875, 885, ( 886 is a NAND gate, and 883 and 884 are OR gates. The operation of this circuit will be described below.

(또는

)가 고레벨일때 출력 C_X(i)(또는 C_Y(j))가 고레벨로 된다. "1"을 기억시킬 때는 퓨즈(882)를 절단한다. 이것에 의해 어드레스가 "1"일때, 즉 참신호 A_X(i)(또는 A_Y(j))가 고레벨, 보조신호

(또는

)가 저레벨일 때에 출력 C_X(i)(또는 C_Y(j))가 고레벨로 된다.When the bit comparison circuit 810 stores "X", the fuse 871 is blown. As a result, the node 890 becomes low level, 891 becomes high level, 892 becomes high level, and 833 becomes low level. Therefore, since the don care signal D is at a high level, the output C _X (i) (or C _Y (j)) is at a high level regardless of the address. When storing "0" or "1", the fuse 871 is not cut. At this time, D is a low level. When storing "0", the fuse 881 is cut off. As a result, when the address is "0", that is, the true signal A _X (i) (or A _Y (j)) is low level, the auxiliary signal.

(or

) Is at high level, output C _X (i) (or C _Y (j)) is at high level. When storing "1", the fuse 882 is blown. As a result, when the address is " 1 ", that is, the true signal A _X (i) (or A _Y (j)) is high level, the auxiliary signal

(or

) Is at the low level, the output C _X (i) (or C _Y (j)) is at the high level.

The characteristic of the circuit of this embodiment is that the number of fuses to be cut even when storing all of "0", "1", and "X" may be one (two in the previous embodiment). This can shorten the time required for defect repair during inspection. Another feature is that although not shown in the figure, the Doncare signal D can be shared by several bit comparison circuits. For example, in order to realize the five substitution methods shown in FIG. 29, the don care signals of A _X (1) to A _X (n _W-3 ) may be common. In such a case, only one set of circuits (871) to (875) needs to be provided, so that the occupied area can be reduced.

[Example 5 of the address comparison circuit]

32 shows a fifth embodiment of the address comparison circuit. The difference from the previous embodiment is the configuration of the bit comparison circuit 810. 901, 911 are laser cut fuses, 902, 912 are N-channel MOS transistors, 903, 913 are inverters, 904, 905, 914, ( 915 denotes NAND gates, 917, 918, 919, and 920 denote P-channel MOS transistors, and 921, 922, 923, and 924 denote N-channel MOS transistors. The operation of this circuit will be described below.

(또는

) 가 고레벨일 때에 출력 C_X(i)(또는 C_Y(j))과 고레벨로 된다. "1"을 기억 시킬때는 퓨즈(911)을 절단한다. 이것에 의해 노드 (932)가 저레벨, 노드(942)가 고레벨로 된다. 따라서, 어드레스가 "1"일때, 즉 참신호 A_X(i)(또는 A_Y(j))가 고레벨, 보조신호

(또는

)가 저레벨일 때에 출력 C_X(i)(또는 C_Y(j))가 고레벨로 된다.When the fuses 091 and 911 are not all cut off, the nodes 932 and 942 are at the low level. Thus, regardless of the address, the output C _X (i) (or C _Y (j)) of the bit comparison circuit 810 is at a high level. This is a state where "X" is memorized. When storing "0", the fuse 901 is cut off. As a result, the node 932 becomes high level and 942 becomes low level. Therefore, when the address is "0", that is, the true signal A _X (i) (or A _Y (j)) is at a low level, the auxiliary signal

(or

) Is at the high level with the output C _X (i) (or C _Y (j)). When storing "1", the fuse 911 is cut off. As a result, the node 932 becomes low level and the node 942 becomes high level. Therefore, when the address is "1", that is, the true signal A _X (i) (or A _Y (j)) is high level, the auxiliary signal

(or

) Is at the low level, the output C _X (i) (or C _Y (j)) is at the high level.

The feature of this embodiment is that the number of fuses is smaller than that of the previous two embodiments, and therefore the occupation area can be reduced. In addition, since the fuse need not be cut when storing "X", the time required for defect repair can be further shortened than in the previous embodiment.

Another feature is that the address comparison circuit can be invalidated by cutting both the fuses 901 and 911. At this time, since C _X (i) (or C _Y (j)) is always low level, YR is always low level. The function can be used when the spare memory cell in which the regular memory cell is replaced is defective. For example, it is assumed that SB (0) was bad as a result of using the address comparison circuit AC (0) to replace the bad bit line with the spare bit line SB (0) in the semiconductor memory of FIG. In this case, the SB (0) may be invalidated by the above method, and instead, the ACB may be replaced by the spare bit line SB (1), for example.

In Examples 3 to 5 of the address comparison circuit described above, all the bit comparison circuits can store the don care value " X ". However, some bit comparison circuits do not need to store "X". For example, in order to realize the five substitution methods shown in Fig. 29, it is not necessary to store "X" in the bit comparison circuit for A _Y (0) to A _Y (n _B-1 ). In such a case, the bit comparison circuit for A _Y (0) to A _Y (n _B-1 ) can use the circuit which cannot store "X", for example, the circuit shown in FIG. We can plan. For example, in the case where only three substitution methods in the third to fifth columns of FIG. 29 are realized (that is, no substitution is performed on a bit basis or bit pair basis), the following may be performed. For A _Y (0) to A _Y (n _B-1 ), using a bit comparison circuit that can store "X" only 2 bits of A _X (n _w-2 ) and A _X (n _w-1 ) A comparison comparison circuit that cannot store the letter "X" is used. The bit comparison circuit for A _X (0) to A _X (n _W-3 ) is unnecessary.

Example 10

33 shows an embodiment of FIG. 10 of the present invention. The main memory MM, the central processing unit CPU, and the input / output circuit I / O are provided on one chip. When the main memory MM is composed of the memories of the above-described embodiments 1 to 9, the efficiency as a chip is remarkably improved.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example, Of course, it can be variously changed in the range which does not deviate from the summary.

According to the present invention, the number of memory cells to be replaced at the same time by the defect repair is reduced, the probability that the spare memory cell itself is defective is reduced, and the utilization efficiency of each memory cell is high. In addition, since the degree of freedom of setting the preliminary bow and the address comparison circuit of each memory mat is increased, there is an effect that a defect repair circuit having a large effect of improving efficiency in a small area can be made.

Claims (18)

A plurality of word lines W [i, 0] -W [i, 3] and a plurality of bit lines B [i, 0] -B [i, 3] formed so that intersection points are formed between the word lines and the bit lines ), A memory cell provided at a desired one of the intersection points, a memory array having a plurality of spare word lines SW [k, 0] -SW [k, 3], and a bad word line address present in the memory array, respectively. A plurality of address comparison means AC [k] for comparing the stored addresses with respective addresses to be accessed, and means for replacing defective word lines with spare word lines in accordance with one output of each of the plurality of address comparison means. (501,504), wherein the memory array is divided into M (M &gt; 2, M is an integer) memory mats 100-103, 130-133, and word lines thereof are each replaced with spare word lines at the same time. The number m is a divisor of M less than M, which is logical in each of the M memory mats. As the number corresponding to the number of independent spare word line L by and, when R as the number corresponding to the number of the address comparison means, the semiconductor memory to satisfy a relationship of L <R <LM / m. The semiconductor memory according to claim 1, wherein the word line is activated in accordance with one output of said plurality of address comparison means indicating a logical match between the word line to be accessed and the stored bad word line address. The method of claim 1, wherein the R address comparing means is a multiple of the L group, and each one of them is applied to each one of the L means for performing a logical sum of the outputs of the R / L address comparing means. One of each of the L groups is combined, and L signals representing a logical sum in each of the L groups output from the L means are used to select a spare word line in each memory mat. A plurality of word lines W [i], a plurality of bit lines B [j] provided such that intersection points are formed between the word lines and bit lines, and memory cells M [i, J] provided in one desired of the intersection points ), A memory array 10 having a plurality of spare memory cells, and a plurality of address comparison means (AC [0]-), each storing a bad address existing in the memory array and comparing the stored bad address with each address to be accessed. AC [3]) and means (504, 506) for replacing memory cell groups having bad memory cells with spare memory groups according to the comparison results by the plurality of address comparison means, each of the plurality of address comparison means. One has a plurality of bit comparing means, each of the bit comparing means has a ROM and receives a bit of an address signal and outputs a coincidence signal according to the bit of the ROM and the address signal. And at least one of the bit comparison means stores the ternary value of the logical value 0, the logical value 1, and the doncare value, and the bits of the data and the address signal stored in the ROM are logical values 0, Or the coincidence signal is output from the ROM when the bits of the data and the address signal stored in the ROM are a logic value 1 or the data stored in the ROM is a doncare value. The semiconductor memory according to claim 4, wherein the semiconductor memory is a dynamic random access memory having a storage capacity of 16 megabits or more. 5. The memory array of claim 4, wherein the memory array is divided into several memory mats 130-133, each group of memory mats being in common with the decoder 40 to select one of its bits. A plurality of address bits indicating one of the plurality of memory mats having a ROM for storing ternary data of a logical value 0, a logical value 1, and a doncare value, and commonly using the decoder. A semiconductor memory which one bit comparison means receives. 5. The memory array according to claim 4, wherein the memory array is divided into several memory mats 130-133, each group of memory mats having a common decoder 40 for selecting a signal on its respective bit line. And an address bit indicating one mat of the plurality of memory mats having a ROM for storing ternary data of a logic value 0, a logic value 1, and a don care value and using a sense circuit in common. A semiconductor memory received by one of several bit comparison means. A plurality of word lines W [i, 0] -W [i, 3] and a plurality of bit lines B [j, 0] -B [i, 3] formed so that intersection points are formed between the word lines and the bit lines ), A memory cell provided at the desired one of the intersection points, a memory array having a plurality of spare bit lines SB [k, 0] -SB [k, 3], and a bad bit line address present in the memory array, respectively. A plurality of address comparison means (AC [k]) for comparing the stored addresses with respective addresses to be accessed, and replacing the bad bit lines with spare bit lines in accordance with one output of each of the plurality of address comparison means. Means 504, wherein the memory array is divided into M (M &gt; 2, M is an integer) memory mats, and the number m of memory mats whose bit lines are each replaced with spare bit lines at a time is less than M Is a divisor of M and is logically independent of each one of the M memory mats A semiconductor memory that satisfies the relationship L <R <LM / m when a number corresponding to the number of spare bit lines is L and a number corresponding to the number of address comparison means is R. 9. The semiconductor memory according to claim 8, wherein a spare bit line is activated in accordance with one output of said plurality of address comparison means indicating a logical match between a bit line to be accessed and a stored bad bit line address. 9. The R address comparison means according to claim 8, wherein the R address comparison means is a multiple of the L group, and each one of them is applied to each one of the L means for performing a logical sum of the outputs of the R / L address comparison means. One of each of the L groups is combined, and L signals output from the L means and representing a logical sum in each of the L groups are used to select a spare bit line in each memory mat. 9. The semiconductor memory according to claim 8, wherein the semiconductor memory is used in a microcomputer so that access of the memory is executed via a bus, and the microcomputer and the memory are formed on one chip. 11. The semiconductor memory according to claim 10, wherein each one of said L means for performing a logical sum comprises a logical OR circuit. The semiconductor memory according to claim 1, wherein the semiconductor memory is a dynamic random access memory having a storage capacity of 16 megabits or more. A semiconductor memory according to claim 3, comprising a logical OR circuit of each of said L means for performing a logical sum. The semiconductor memory according to claim 13, wherein said memory is used via a bus by said memory being used in a microcomputer. 6. The semiconductor memory according to claim 5, wherein the memory is accessed via a bus by using the memory in a microcomputer. The semiconductor memory according to claim 15, wherein the microcomputer and the semiconductor memory are formed on one chip. The semiconductor memory according to claim 16, wherein the microcomputer and the semiconductor memory are formed on one chip.

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