KR900006973A - Semiconductor Memory with Fault Relief Circuit - Google Patents

Abstract

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Description

Semiconductor Memory with Fault Relief Circuit

Since this is an open matter, no full text was included.

9 and 10 illustrate a first embodiment of the present invention.

Claims (17)

A memory array having memory cells arranged in necessary portions among a plurality of word lines, a plurality of bit lines arranged to intersect the plurality of word lines, and intersections of the plurality of word lines and a plurality of bit lines, several spare word lines, or spare bits Address comparison means for storing a bad address in the memory array and comparing it with an address requested for access, and a word line or a bit line including a bad memory cell according to the comparison result as the spare word line or the spare bit line. A semiconductor memory having means for replacing, wherein the memory array includes M pieces (M The number m of word lines or bit lines, which are divided into memory mats of 2) and replaced at the same time, is a divisor of M less than M, the number L of spare word lines or spare bit lines per memory mat, and the number R of the address comparison means R. L <R between the number M of divisions and the number m of word lines or bit lines to be replaced A semiconductor memory having a defect repair circuit, wherein a relationship of LM / m is established. The semiconductor memory according to claim 1, wherein the correspondence relationship between said address comparing means and said spare word line or spare bit line is variable. The method according to claim 1, wherein R is a multiple of L, and L signals obtained by performing a logical sum of R / L comparison results of R address comparison means are assigned to the reserved word line or the reserved bit line of each memory mat. A semiconductor memory having a defect repair circuit, which is used for selection. A memory array having a plurality of word lines, a plurality of bit lines arranged to intersect the plurality of word lines, a memory cell provided at a required portion of intersections of the plurality of bit lines and a plurality of word lines, several spare word lines, several spare bits An address comparison means for storing a line, a plurality of spare memory cells, a bad address in the memory array and comparing it with an address requested for access, and means for replacing a memory cell group including a bad memory cell with a spare memory cell group according to the comparison result. 2. A semiconductor memory having a defect repair circuit according to claim 1, wherein said address comparing means can prevent the corresponding bits from being compared for at least one bit of an address. The semiconductor memory device according to claim 4, wherein the memory array is divided into a plurality of memory mats, and at least part of a circuit along a bit line is shared by the plurality of memory mats. The semiconductor memory having a defect relief circuit can be arranged so as not to compare address bits identifying memory mats sharing the circuit. 6. The semiconductor memory according to claim 5, wherein the circuit according to the bit line is a decoder for selecting a bit line. The semiconductor memory according to claim 5, wherein the circuit along the bit line is a sense circuit for amplifying a signal on the bit line. A memory array having memory cells arranged in necessary portions among a plurality of word lines, a plurality of bit lines arranged to intersect the plurality of word lines, an intersection point of the plurality of word lines and a plurality of bit lines, a plurality of spare word lines, or a reserve bit Address comparison means for storing a bad address in the memory array and comparing it with an address requested for access, and a word line or a bit line including a bad memory cell according to the comparison result as the spare word line or the spare bit line. A semiconductor memory having a means for replacing, wherein the word line address is compared at least in the address comparison means for determining the replacement of the bit line, or at least the bit line address is compared in the address comparison means for determining the replacement of the word line. Semiconductor memo with fault relief circuit . The semiconductor memory according to claim 1, wherein the semiconductor memory is a dynamic random access memory and has a storage capacity of 16 Mbit or more. 5. The semiconductor memory according to claim 4, wherein the semiconductor memory is a dynamic random access memory and has a storage capacity of 16 Mbit or more. 9. The semiconductor memory according to claim 8, wherein said semiconductor memory is a dynamic random access memory and has a storage capacity of 16 Mbit or more. A microcomputer using the semiconductor memory according to claim 9. A microcomputer using the semiconductor memory according to claim 10. A microcomputer using the semiconductor memory according to claim 11. The microcomputer according to claim 12, wherein the microcomputer and the semiconductor memory are formed on one chip. The microcomputer according to claim 13, wherein the microcomputer and the semiconductor memory are formed on one chip. The microcomputer according to claim 14, wherein the microcomputer and the semiconductor memory are formed on one chip. ※ Note: The disclosure is based on the initial application.