KR930004857Y1 - Bread board for standard ic package and shrink ic package - Google Patents
Bread board for standard ic package and shrink ic package Download PDFInfo
- Publication number
- KR930004857Y1 KR930004857Y1 KR2019900010329U KR900010329U KR930004857Y1 KR 930004857 Y1 KR930004857 Y1 KR 930004857Y1 KR 2019900010329 U KR2019900010329 U KR 2019900010329U KR 900010329 U KR900010329 U KR 900010329U KR 930004857 Y1 KR930004857 Y1 KR 930004857Y1
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- South Korea
- Prior art keywords
- package
- standard
- shrink
- lead
- breadboard
- Prior art date
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
내용 없음.No content.
Description
제1a도 및 b도는 통상적인 표준형 IC 패키지 및 슈링크형 IC 패키지의 사사시도.1A and B are perspective views of conventional standard IC packages and shrink IC packages.
제2도는 본 고안에 의한 브레드 보드의 평면도.2 is a plan view of the bread board according to the present invention.
제3a도는 제2a도부 확대도, b도는 제2도의 B부 확대도.3a is an enlarged view of part 2a, and b is an enlarged view of part B of FIG.
제4도는 일반적인 브레드 보드의 평면도.4 is a plan view of a typical breadboard.
제5도는 제4도 C부 확대도.5 is an enlarged view of part C of FIG.
＊ 도면의 주요부분에 대한 부호의 설명＊ Explanation of symbols on main parts of drawing
1 : 표준형 IC 패키지 2, 4 : 리드1: Standard IC Package 2, 4: Lead
3 : 슈링크형 IC 패키지 10, 11 : 유니트3: Shrink IC package 10, 11: Unit
10a, 11a : 리드 삽입공10a, 11a: lead insertion hole
본 고안은 IC 패키지(package)의 특성을 실험하고 분석하기 위하여 IC 패키지가 결합되는 브레드 보드(bread board)에 관한 것으로, 특히 표준형 IC 패키지 (standard IC package)와 리드(lead) 사이의 간격이 좁은 슈링크형 IC 패키지(shrink IC package)를 동시에 결합할 수 있게 한 표준형 IC 패키지 및 슈링크형 IC 패키지 겸용 브레드 보드에 관한 것이다.The present invention relates to a bread board to which the IC package is combined to test and analyze the characteristics of the IC package. In particular, the gap between the standard IC package and the lead is narrow. The present invention relates to a breadboard for both a standard IC package and a shrunk IC package that enables simultaneous coupling of a shrink IC package.
일반적으로 제1a도에 도시한 바와 같이, 표준형 IC 패키지(1)는 각 리드(2) 사이의 간격(d)이 100mil(1mil=25.4㎛)로 유지되어 있고, 제1b도에 도시한 바와 같이, 슈링크형 IC 패키지(3)는 각 리드(4) 사이의 간격(d')이 70mil로 유지되어 있다.In general, as shown in FIG. 1A, the standard IC package 1 has a space d between each lead 2 at 100 mils (1 mil = 25.4 mu m), as shown in FIG. 1B. In the shrink type IC package 3, the distance d 'between each lead 4 is maintained at 70 mils.
한편, 실험실에서 표준형 IC 패키지(1) 및 슈링크형 패키지(2)의 특성 실험 및 분석을 하기 위하여 사용되는 제4도 및 제5도에 도시한 바와 같은 브레드 보드(5)는 표준형 IC 패키지(1)의 리드(2)가 결합될 수 있도록 리드 삽입공(6a)이 100mil의 간격(d)을 두고 2열 또는 4열로 천공된 수개의 유니트(6)가 배치되어 있으며, 상기 브레드 보드(5)에 표준형 IC 패키지(1)를 결합시킨 상태에서 각종 회로를 구성하여 특성실험 및 분석을 하게 된다.On the other hand, the breadboard (5) as shown in Figures 4 and 5 used for the characterization and analysis of the standard IC package (1) and the shrink-type package (2) in the laboratory is a standard IC package ( In order to allow the lead 2 of 1) to be coupled, several units 6 having two or four rows of lead insertion holes 6a are arranged at intervals of 100 mils, and the breadboard 5 In the state in which the standard IC package (1) is combined with each other, various circuits are configured to perform characteristic experiments and analysis.
그러나 상기한 바와 같은 종래의 브레드 보드(5)는 리드 삽입공(6a)이 100mil의 간격(d)을 두고 형성되어 있으므로 표준형 IC 패키지(1)만 결합시킬 수 밖에 없는 단점이 있었으며, 이에 따라 슈링크형 IC 패키지(3)를 실험할 경우에는 그의 리드(4)에 별도의 와이어를 납땜고정하여 브레드 보드(5)에 연결하여야 함으로써 작업이 용이하지 못하고 실험결과가 부정확하며, 실험후 납땜을 다시 제거시켜야 하는 등 여러 문제점이 있었다.However, the conventional bread board 5 as described above has a disadvantage in that only the standard IC package 1 can be combined because the lead insertion holes 6a are formed at intervals of 100 mils. In the case of experimenting with the link type IC package 3, a separate wire must be soldered to its lead 4 to be connected to the bread board 5, so that the operation is not easy and the result of the experiment is inaccurate. There were several problems, including the need to remove them.
본 고안은 상기한 바와 같은 종래의 문제점을 해소하기 위하여 안출한 것으로, 브레드 보드에 슈링크형 IC 패키지의 리드가 결합되는 간격이 좁은 리드삽입공을 형성함으로써 표준형 IC 패키지는 물론 리드사이의 간격이 좁은 슈링크형 IC 패키지도 별도의 작업없이 브레드 보드에 결합시켜 특성실험 및 분석을 실시할 수 있도록 구성한 것인바, 이하 본 고안을 첨부된 도면에 의하여 설명하면 다음과 같다.The present invention has been devised to solve the above-mentioned problems, and the gap between the leads as well as the standard IC package is formed by forming a narrow lead insertion hole in which the leads of the shrink type IC package are coupled to the breadboard. The narrow shrink type IC package is also configured to be coupled to the breadboard without any additional work to perform the characteristic experiments and analysis. Hereinafter, the present invention will be described with reference to the accompanying drawings.
제2도 및 제3도에 도시된 바와 같이, 표준형 IC 패키지(1)의 리드(2)가 삽입되는 리드 삽입공(10a)이 일정간격을 두고 수개의 열로서 형성된 수개의 유니트(10)가 배치되는 브레드 보드(20)에 있어서, 상기 유니트(10)의 사이에 슈링크형 IC 패키지(3)의 리드(4)가 삽입될 수 있도록 수개의 리드 삽입공(11a)이 일정간격(d')을 두고 수개의 열로서 형성된 유니트(11)를 배치하여 구성한 것이다.As shown in FIG. 2 and FIG. 3, several units 10 are formed in several rows with lead insertion holes 10a into which leads 2 of the standard IC package 1 are inserted. In the breadboard 20 arranged, several lead insertion holes 11a are spaced d 'so that the leads 4 of the shrink type IC package 3 can be inserted between the units 10. It is configured by arranging the unit 11 formed in several rows with the ().
상기한 바와 같이 구성되는 본 고안에 의한 브레드 보드(20)는 표준형 IC 패키지(1)의 리드(2)가 삽입되는 100mil 간격(d)의 리드삽입공(10a)으로 구성된 유니트(10)와, 슈링크형 IC 패키지(3)의 리드(4)가 삽입되는 리드삽입공(11a)으로 구성된 유니트(11)가 여러개로 배치되어 있으므로 그 각각의 유니트(10) (11)에 표준형 IC 유니트(1) 및 슈링크형 IC 패키지 (3)를 각각 결합하여 동시에 특성실험 및 분석을 할 수 있는 것이다.Breadboard 20 according to the present invention is configured as described above is a unit 10 consisting of a lead insertion hole (10a) of 100mil spacing (d) is inserted into the lead 2 of the standard IC package (1), Since a plurality of units 11 composed of lead insertion holes 11a into which the leads 4 of the shrunk IC package 3 are inserted are arranged, a plurality of standard IC units 1 are provided in each of the units 10 and 11. ) And Shrink IC package (3) can be combined to perform characterization and analysis at the same time.
이상에서 설명한 바와 같은 본 고안에 의한 브레드 보드는 슈링크형 IC 패키지의 리드를 삽입하기 위한 간격이 좁은 리드삽입공을 형성하여, 표준형 IC 패키지와 슈링크형 IC 패키지를 겸용으로 사용할 수 있게 함으로써 종래의 경우와 같은 작업의 번거로움 및 실험의 부정확함을 배제하여 보다 용이하고 정확하게 슈링크형 IC 패키지를 검사하는 효과가 있다.As described above, the bread board according to the present invention forms a narrow lead insertion hole for inserting a lead of a shrink type IC package, thereby allowing a standard IC package and a shrink type IC package to be used in combination. By eliminating the troublesome work and the inaccuracy of the experiment, it is possible to inspect the shrunk IC package more easily and accurately.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900010329U KR930004857Y1 (en) | 1990-07-13 | 1990-07-13 | Bread board for standard ic package and shrink ic package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019900010329U KR930004857Y1 (en) | 1990-07-13 | 1990-07-13 | Bread board for standard ic package and shrink ic package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920003422U KR920003422U (en) | 1992-02-25 |
| KR930004857Y1 true KR930004857Y1 (en) | 1993-07-23 |
Family
ID=19301034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019900010329U KR930004857Y1 (en) | 1990-07-13 | 1990-07-13 | Bread board for standard ic package and shrink ic package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR930004857Y1 (en) |
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1990
- 1990-07-13 KR KR2019900010329U patent/KR930004857Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR920003422U (en) | 1992-02-25 |
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