KR940005204A - Stacked mounting system of semiconductor package - Google Patents

Stacked mounting system of semiconductor package Download PDF

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Publication number
KR940005204A
KR940005204A KR1019920014432A KR920014432A KR940005204A KR 940005204 A KR940005204 A KR 940005204A KR 1019920014432 A KR1019920014432 A KR 1019920014432A KR 920014432 A KR920014432 A KR 920014432A KR 940005204 A KR940005204 A KR 940005204A
Authority
KR
South Korea
Prior art keywords
holes
package
row
mounting system
plate
Prior art date
Application number
KR1019920014432A
Other languages
Korean (ko)
Inventor
김경섭
권오식
박범렬
정현조
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920014432A priority Critical patent/KR940005204A/en
Priority to JP5195967A priority patent/JPH0714980A/en
Publication of KR940005204A publication Critical patent/KR940005204A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/12—Resilient or clamping means for holding component to structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1015—Plug-in assemblages of components, e.g. IC sockets having exterior leads
    • H05K7/103—Plug-in assemblages of components, e.g. IC sockets having exterior leads co-operating by sliding, e.g. DIP carriers
    • H05K7/1046—J-shaped leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
    • H05K7/1053—Plug-in assemblages of components, e.g. IC sockets having interior leads
    • H05K7/1076—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by sliding
    • H05K7/1084—Plug-in assemblages of components, e.g. IC sockets having interior leads co-operating by sliding pin grid array package carriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

절연 플레이트에 반도체 장치 패키지에 외부 리드들을 삽입시켜 실장하도록, 상기 플레이트는 패키지 리드단자 위치와 동일한 대응 위치에 관통공이 형성되고, 이 관통공들은 상하로 게속하여 적정 간격을 두고 연이어 배치형성되며, 상기 적정 간격에는 패키지와 또 다른 실장된 패키지간 이격된 거리에 대응하고 이 위치에서 또 다른 관통공이 형성되어 방열공을 이루며, 상기 리드 삽입되는 관통공들는 플레이트 표면상에 도전성 라인들로 다른 관통공들과 연결되어 형성된 플레이트인 것을 특징으로 하는 반도체 패키지의 적층형 실장 시스템.The through-holes are formed at the same position as that of the package lead terminal, and the through-holes are continuously formed at appropriate intervals in succession to the plate so that the external leads are inserted into the semiconductor device package and mounted on the insulating plate. At appropriate intervals, the through holes correspond to the spaced distance between the package and another package, and another through hole is formed at this position to form a heat dissipation hole. Stacked mounting system of a semiconductor package, characterized in that the plate formed in connection with.

Description

반도체 패키지의 적층형 실장 시스템Stacked mounting system of semiconductor package

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3 (a)와 (b)본 발명에 따라 한쌍의 플레이트 내에 적층형으로 반도체 패키지를 장착한 상태를 나타낸 측면도 및 플레이트의 사시도,A side view and a perspective view of a plate, in which a semiconductor package is mounted in a pair of plates in a pair of plates according to the present invention (a) and (b),

제4도는 플레이트가 소켓에 장착되는 상태를 나타내는 조립도, 제5도는 다른 타입인 금속패프를 갖는 플레이트의 사시도.4 is an assembled view showing a state in which the plate is mounted to the socket, and FIG. 5 is a perspective view of a plate having a metal pad of another type.

Claims (3)

절연 플레이트에 반도체 장치 패키지에 외부 리드들을 삽입시켜 실장하도록, 상기 플레이트는 패키지 리드단자 위치와 동일한 대응 위치에 관통공이 형성되고, 이 관통공들은 상하로 게속하여 적정 간격을 두고 연이어 배치형성되며, 상기 적정 간격에는 패키지와 또 다른 실장된 패키지간 이격된 거리에 대응하고 이 위치에서 또 다른 관통공이 형성되어 방열공을 이루며, 상기 리드 삽입되는 관통공들은 플레이트 표면상에 도전성 라인들로 다른 관통공들과 연결되어 형성된 플레이트인 것을 특징으로 하는 반도체 패키지의 적층형 실장 시스템.The through-holes are formed at the same position as that of the package lead terminal, and the through-holes are continuously formed at appropriate intervals in succession to the plate so that the external leads are inserted into the semiconductor device package and mounted on the insulating plate. At appropriate intervals, the through holes correspond to the spaced distance between the package and another package, and another through hole is formed at this position to form a heat dissipation hole. Stacked mounting system of a semiconductor package, characterized in that the plate formed in connection with. 제1항에 있어서, 상기 실장되는 패키지는 리드가 걸윙 또는 J-밴드형인 것로 솔더링에 의해 실장됨을 특징으로 하는 반도체 패키지의 적측형 실장 시스템.The system of claim 1, wherein the package to be mounted is mounted by soldering as a lead having a gull wing or a J-band type. 제1항에 있어서, 상기 리드가 삽입 고정되는 관통공은 로우(row)방향으로 일렬 정렬된 관통공들이며 이들은 컬럼 방향으로 연이어서 형성되는 관통공이고, 상기 로우 방향 관통공들 사이에는 동일 방향의 다수의 방열공들이 형성되며, 컬럼 방향으로 리드 삽입용 관통공 끼리의 금속 라인으로 연결됨을 특징으로 하는 반도체 패키지 적측형 실장 시스템.According to claim 1, wherein the through-holes through which the lead is inserted and fixed are through-holes arranged in a row direction in a row (row) are the through-holes are formed successively in the column direction, the row in the same direction between the through-holes A plurality of heat dissipation holes are formed, the semiconductor package mounting type mounting system, characterized in that connected to the metal line between the through holes for the lead insertion in the column direction. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920014432A 1992-08-11 1992-08-11 Stacked mounting system of semiconductor package KR940005204A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920014432A KR940005204A (en) 1992-08-11 1992-08-11 Stacked mounting system of semiconductor package
JP5195967A JPH0714980A (en) 1992-08-11 1993-08-06 Laminated module of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920014432A KR940005204A (en) 1992-08-11 1992-08-11 Stacked mounting system of semiconductor package

Publications (1)

Publication Number Publication Date
KR940005204A true KR940005204A (en) 1994-03-16

Family

ID=19337818

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920014432A KR940005204A (en) 1992-08-11 1992-08-11 Stacked mounting system of semiconductor package

Country Status (2)

Country Link
JP (1) JPH0714980A (en)
KR (1) KR940005204A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410193A (en) * 2021-05-27 2021-09-17 力成科技（苏州）有限公司 8+1 heap chip package device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002305286A (en) 2001-02-01 2002-10-18 Mitsubishi Electric Corp Semiconductor module and electronic component
US20030040166A1 (en) 2001-05-25 2003-02-27 Mark Moshayedi Apparatus and method for stacking integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410193A (en) * 2021-05-27 2021-09-17 力成科技（苏州）有限公司 8+1 heap chip package device
CN113410193B (en) * 2021-05-27 2024-05-03 元成科技(苏州)有限公司 8+1 Stacked chip packaging device

Also Published As

Publication number Publication date
JPH0714980A (en) 1995-01-17

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