KR930004722B1 - Manufacturing method of semiconductor element - Google Patents

Manufacturing method of semiconductor element Download PDF

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KR930004722B1
KR930004722B1 KR1019900003000A KR900003000A KR930004722B1 KR 930004722 B1 KR930004722 B1 KR 930004722B1 KR 1019900003000 A KR1019900003000 A KR 1019900003000A KR 900003000 A KR900003000 A KR 900003000A KR 930004722 B1 KR930004722 B1 KR 930004722B1
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South Korea
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forming
layer
region
collector
electroconductive
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KR1019900003000A
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Korean (ko)
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KR910017665A (en
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안형근
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

The semiconductor device is mfd. by (a) forming a second buried layer (2) and a first electroconductive bottom-isolating layer (3) on the fixed part of the first electroconductive substrate (1), (b) forming a second electroconductive low density epitaxy layer (4) on the whole surface of the substrate (1), (c) etching a fixed part of an isolating layer region and a collector- forming region, (d) forming a first electroconductive top- isolating layer (5) and a second electroconductive collector region (6) on the etched part of the layer (4), (e) forming a first electroconductive base region (7) on the layer (4), (f) forming a second emittor region (8) on the base (7), and (g) forming an insulating film, the collector, the base, the emitter contact window and an electrode.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

제1a도∼i도는 본 발명의 반도체 소자 공정 단면도.1A to i are cross-sectional views of a semiconductor device process of the present invention.

제2도는 종래의 반도체 소자 2가지 공정단면도.2 is a cross-sectional view of two conventional semiconductor devices.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 기판 2 : n+매몰층1: substrate 2: n + buried layer

3 : 하부격리층 4 : 에피층3: lower isolation layer 4: epi layer

5 : 상부격리층 6 : 콜렉터5: upper isolation layer 6: collector

7 : 베이스 8 : 에미터7: base 8: emitter

9 : CVD산화막9: CVD oxide film

본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 고내압 및 고속속자에 적당하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is particularly suitable for high breakdown voltage and high speed flux.

종래에는 제2도에 도시된 바와 같이 P형 기판(1)에 고농도 n형 이온주입으로 n+매몰층(2)을 형성하고 에피층(4)을 성장시킨 후 P형 이온주입으로 격리층(3a)을 형성하였다.Conventionally, as shown in FIG. 2, the n + buried layer 2 is formed on the P-type substrate 1 by the high concentration n-type ion implantation, the epitaxial layer 4 is grown, and the isolation layer is formed by the P-type ion implantation. 3a) was formed.

그리고 P형 이온주입에 의한 베이스(7)와 n형 이온주입에 의한 에미터(8)를 형성하고 콘텍트 및 메탈공정을 실시하거나, 상기 P형기판(1)에서 n+매몰층(2)을 형성한 상태에서 먼저P형 하부격리층(3)을 형성한 후 에피층(4)을 성장시키고 이어 P형 상부격리층(5)을 형성하였으며 이하 상기한 바와 같은 공정을 거쳐서 소자를 제조하였다.And forming a base 7 by P-type implantation and an emitter 8 by n-type implantation and performing a contact and metal process, or n + buried layer 2 on the P-type substrate 1. In the formed state, first, the P-type lower isolation layer 3 was formed, the epi layer 4 was grown, and then the P-type upper isolation layer 5 was formed. The device was manufactured by the following steps.

이와 같이 P형 하부격리층(3a)혹은 상, 하부격리층(3, 5)과 에피층(4) 사이의 접합용량은 에피층(4)의 두께에 따른 격리층(3a, 3, 5)의 면적에 비례하여 증가하였으나 디자인 룰이 작아지고 소자의 면적이 감소함에 따라 속도를 증가시키기 위해서는 기존의 방법과 같은 소자 격리를 할 수 없으며 내압을 증가시키면서 속도를 증가시키기 어려웠다.As described above, the bonding capacity between the P-type lower isolation layer 3a or the upper and lower isolation layers 3 and 5 and the epi layer 4 is determined by the isolation layers 3a, 3 and 5 according to the thickness of the epi layer 4. As the design rule becomes smaller and the area of the device decreases, it is not possible to isolate the device as in the conventional method, and it is difficult to increase the speed while increasing the breakdown voltage.

또한 소자격리 부분의 면적에 의한 접합용량은 속도증가면에서 가장 큰 결점이 되었다.In addition, the bonding capacity caused by the area of the device isolation portion is the biggest drawback in terms of speed increase.

따라서 본 발명은 상기롸 같은 종래의 결점을 감안하여 안출한 것으로 디자인 룰이 감소됨에 따라 내압을 종래와 같이 유지시키는 한편 속도를 증대시킬 수 있게 함으 그 목적으로 한다.Therefore, the present invention has been made in view of the above-mentioned conventional drawbacks, and as the design rule is reduced, it is possible to maintain the internal pressure as in the prior art while increasing the speed.

상기의 목적을 달성하기 위한 본 발명의 반도체 소자제조 방법을 첨부된 도면 제1도를 참조하여 상세히 설명하면 다음과 같다.The semiconductor device manufacturing method of the present invention for achieving the above object will be described in detail with reference to FIG. 1.

먼저 제1a도와 같은 P형 기판(1)상의 소정부위에 제1b도와 같이 고농도 n형 이온주입으로 n+매몰층(2)을 형성하고 제1c도와 같이 n+매몰층(2) 양측에 n+매몰층과 격리되도록 P형 이온주입으로 하부격리층(3)을 형성한다.First claim in a high-concentration n-type ion implantation, as the 1b help the predetermined portion n + buried layer 2 and n + buried layer, such as help claim 1c form a (2) either side on the P type substrate 1 as 1a help n + The lower isolation layer 3 is formed by P-type implantation so as to be isolated from the buried layer.

그리고 제1d도와 같이 에피층(4)을 성장시키고 제1e도와 같이 건식 또는 습식 식각에 의해 일측 하부격리층(3) 상부와 콜렉터가 형성된 부위의 상측 에피층(4)을 소정깊이로 식각한다.As shown in FIG. 1D, the epi layer 4 is grown, and as shown in FIG.

다음에 제1f도와 같이 P형 이온주입으로 하부격리층(3)상의 에피층(4)에 P형 상부격리층(5) 영역을 형성하고 제1g도와 같이 고농도 n형(n+) 이온주입으로 콜렉터(6)를 형성함과 함께 제1h도와같이 B 또는 BF2의 이온주입으로 베이스(7)을 형성한다.Next, a P-type upper isolation layer 5 region is formed on the epitaxial layer 4 on the lower isolation layer 3 by P-type implantation as shown in FIG. 1F, and a high concentration n-type (n + ) ion implantation is performed as shown in FIG. While forming the collector 6, the base 7 is formed by ion implantation of B or BF 2 as shown in FIG. 1h.

이후 CVD 산화막(9)을 디포지션 후 어닐링(Annealing)을 실시하고 상기 베이스(7)에 As 이온주입으로 에미터(8)를 형성하며 제1i도와 같이 각 영역(베이스, 에미터, 콜렉터)에 콘택을 형성하고 금속공정을 실시한다.After the deposition of the CVD oxide film 9, annealing is performed, and the emitter 8 is formed by the implantation of As ions into the base 7, and in each region (base, emitter, collector) as shown in FIG. A contact is formed and a metal process is performed.

여기서, 상기 에피층(4)의 두께는 원하는 브레이크 다운을 견딜 수 있게 조절할 수 있으며, 또한 에피층(4)식각의 깊이는 소자의 에피층(4)대 격리층(5)면적에 의한 최소 접합 용량을 갖고 또 접합용량의 설정치에 따라 가변할 수 있다.Here, the thickness of the epi layer 4 can be adjusted to withstand the desired breakdown, and the depth of etching of the epi layer 4 is the minimum junction by the area of the epi layer 4 to the isolation layer 5 of the device. It has a capacity and can vary according to the set value of the junction capacity.

상기와 같이 반도체 소자를 제조하면 업-다운 소자격리 방법의 장점인 디자인 룰의 감소 및 상부격리층(5)형성시 시간이 단축되어 n+매몰층(2)에서 에피층(4)으로서 n형 불순물 확산을 줄여주므로써 브레이크 다운 전압을 줄일 수 있어 소자의 내압 증가를 실현시킬 수 있으며, 또한 동일한 에피층(4) 두께에 비하여 콜렉터 영역을 식각하므로 CCS(Capacitace of Collector-기판)의 감소를 가져올 수 있어서 이로인한 소자의 동작속도가 상대적으로 증가될 수 있는 효과가 있다.The fabrication of the semiconductor device as described above reduces the design rule, which is an advantage of the up-down device isolation method, and shortens the time when the upper isolation layer 5 is formed, and thus n-type as the epi layer 4 in the n + buried layer 2. By reducing impurity diffusion, the breakdown voltage can be reduced, thereby increasing the breakdown voltage of the device, and also reducing the CCS (Capacitace of Collector-substrate) by etching the collector region compared to the same epilayer 4 thickness. As a result, the operation speed of the device can be relatively increased.

Claims (1)

제1도전형 기판(1)의 소정부위에 제2도전형 매몰층(2)과 제1도전형 하부격리층(3)을 형성하는 공정과, 상기 기판(1)전면에 저농도 제2도전형 에피층(4)을 형성하는 공정과, 상기 에피층(4) 표면의 격리층 영역과 콜렉터 형성 영역의 일정부위를 소정깊이로 식각하는 공정과, 상기 에피층(4)의 식각부위에 제1도전형 상부격리층(5)과 제2도전형 콜렉터(6)영역을 형성하는 공정과, 상기 에피층(4)에 제1도전형 베이스(7)영역을 형성하는 공정과, 상기 베이스(8)영역내에 제2도전형 에미터(8) 영역을 형성하는 공정과, 전 표면에 절연막을 형성하고 콜렉터(6), 베이스(7), 에미터(8) 접촉창을 형성하고 전극을 형성하는 공정을 포함하여 제조됨을 특징으로 하는 반도체 소자 제조방법.Forming a second conductive buried layer (2) and a first conductive lower isolation layer (3) on a predetermined portion of the first conductive substrate (1), and the second conductive type having a low concentration on the entire surface of the substrate (1). Forming an epitaxial layer 4, etching a predetermined portion of the isolation layer region and the collector formation region on the surface of the epitaxial layer 4 to a predetermined depth, and forming a first layer on the etching portion of the epitaxial layer 4; Forming a conductive upper isolation layer (5) and a second conductive collector (6) region, forming a first conductive base (7) region in the epi layer (4), and the base (8) Forming a second conductive type emitter (8) region in the region, forming an insulating film on the entire surface, forming a contact window for the collector (6), the base (7), the emitter (8), and forming an electrode; Method of manufacturing a semiconductor device comprising the step of manufacturing.
KR1019900003000A 1990-03-07 1990-03-07 Manufacturing method of semiconductor element KR930004722B1 (en)

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