KR930004529Y1 - Handamard converter for data compresion - Google Patents

Abstract

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Description

Adama converter for data compression

1 is a block diagram of the present invention.

2 is a timing chart for the control of FIG.

3a and 3b are signal waveform diagrams before and after the Adama transformation.

4 is an explanatory diagram showing an algorithm of adama transformation.

* Explanation of symbols for main parts of the drawings

10: A / D converter 20,80: demultiplexer

31-38, 51-58, 91-98: Latch circuit 41-44, 71-73: Adder and subtractor

61-64: Multiplexer 101-104: Data Coder

The present invention relates to a Hadamard converter which can be used for a digital VTR or a real time image processing apparatus. In particular, it is necessary to compress data due to the limitation of the amount of information that can be recorded or required for high speed. The present invention relates to an Adama converter for data compression that enables real-time processing of data with a simple circuit configuration when present.

Recently, in a recording medium such as a digital VTR, an image signal and a video signal are converted and processed, and it is difficult to record and convert all video signals into digital signals in real time, and the amount of information that can be recorded. Because of this limitation, there is a need to compress the data.

Therefore, there may be various conversions for data compression, but the Aadamal conversion is most suitable for the realization of simple hardware for fast recording and reduction of data for data compression.

In general, a transform is composed of a matrix.

That is, if the matrix to be transformed is F (j, k)

Can be displayed as

Here, if j and k are 8, it becomes an 8th order (8x8) matrix.

An Adama transform is an eighth order Adama transform matrix of the matrix to be transformed.

Multiply by

In other words, the transformed matrix f (u, u)

to be.

However, such a matrix-based method requires a large number of multipliers in the circuit configuration, and has a drawback in that the hardware configuration is complicated. In addition, the conversion time is long, and therefore, the system cannot be used in a system requiring high-speed processing.

The present invention has been devised to solve the above-mentioned drawbacks. By solving the matrix and adding and subtracting the calculation, it is possible to implement simple hardware by adding and subtracting or latching circuits. It will be reduced to half to enable a high speed data processing, when the present invention will be described with reference to the accompanying drawings as follows.

1 is a block diagram of the present invention, in which an A / D converter 10 converts an analog video signal into a digital signal according to a sampling clock pulse, and each latch for calculating the digitalized video data. A demultiplexer 20 and a latch circuit 31 to 38 stored in a latch circuit, and output data of the latch circuit 31 to 38 according to the presence or absence of an addition signal for performing a conversion algorithm. And a control signal from among the adder and subtracter 41-44 to subtract, the latch circuit 51-58 which temporarily stores the added and subtracted data for the next operation, and the output data of the latch circuit 51-58. A multiplexer 61-64 for selecting and outputting one data according to the above, an adder and subtractor 71-73 for adding and subtracting the output data of the multiplexer 61-64 to perform a conversion algorithm, and For coding A data coder for reducing the number of bits of the converted data output from the demultiplexer 80 and the latch circuits 91-98 for separating and temporarily storing the added and subtracted data, and correcting and coding the data. Data coder; 101-104.

If described in detail with reference to the timing chart of Figure 2 the effect of the present invention configured as described above.

In general, the matrix form of the 8th order Adama transform is as follows.

Therefore, in the case of the video signal as shown in FIG. 3a, when the conversion is performed by the Adama matrix, a predetermined bit of information is compressed as shown in FIG. 3b. It is possible to reduce the number of bits by half than the received signal.

Where y (0) is about 8 bits, y (2), y (4), y (6) is 4-5 bits, y (1), y (3), y (5), y (7) ) Is compressed in 2-3 bits.

Also, an algorithm for realizing the Adama transform is shown in FIG. 4, and the first embodiment is implemented in hardware.

When an analog video signal as shown in FIG. 2 is applied to the A / D converter 10, the signal is applied as shown in FIG. 2 by the sampling clock pulse of FIG. 2 applied through the clock terminal CLK. It is converted into a digital signal in the form of bit data and output.

The digital signal is applied to the demultiplexer 20 to decompose data to the latch circuits 31 to 38. In the demultiplexer 20, the control signals a ₀ , b ₀ , and c ₀ are used. Optionally, data is sequentially applied to each latch circuit 31-38, and the latch circuit 31-38 stores the data until a latch sino is applied for operation. When the latch signals LAT ₀ -LAT ₇ are applied to the latch circuits 31-38 with a time difference as shown in FIG. 2 through the latch terminal LAT, they are stored in the latch circuits 31-38 accordingly. The added data is applied to each adder and subtractor 41-44 to perform the operation corresponding to x → t in the algorithm of FIG.

The addition and subtraction units 41-44 alternately add and subtract according to the presence or absence of the addition signals ADD ₀ -ADD ₃ as shown in FIG. 2 applied through the addition terminal ADD. If an addition signal is applied to the adder and subtractor 41-44, the addition operation is performed. If the addition signal is not applied, the addition operation is performed.

As the addition and subtraction proceed alternately as described above, the output data of the addition and subtraction parts 41-44 are sequentially applied to each latch circuit 51-58, which is temporarily applied to the latch circuit 51-58. The stored data are sequentially output as the latch signals LAT _{8 to} LAT ₁₅ as shown in FIG. 2 are applied to the multiplexers 61 to 64, and the multiplexers 61 to 64 control terminals. Data is selected and output according to the control signals d ₀ , e ₀ , f ₀ , g _{0 of} FIG. 2 applied through (CS).

The data selectively output as described above is applied to the adder and subtractor 71 and 72 to perform an operation corresponding to t → z in the algorithm of FIG. 4, and the add and subtract operations are alternately performed as described above. Accordingly, the output data are sequentially supplied to the adder and subtractor 73 to perform the operation corresponding to z → y in the algorithm of FIG. 4 to perform the last operation.

After completion of the addition and subtraction operations, the output data is distributed by the demultiplexer 80 and applied to each latch circuit 91-98. As shown in FIG. 4, the converted data are output in a different order. Therefore, when the data stored in the latch circuits 91-98 are coded, this order is corrected, and when the stored data are output in accordance with the latch signals LAT _16- LAT _{23 of} FIG. By taking only bits, y (0) is input to the data coder 101 by eight bits, and y (1), y (2), y (3) and y (3), y (4) and y (5) are applied by 2, 4, and 2 bits, respectively, and y (6) and y (7) are applied by 4 bits to the data coder 104, respectively.

In this case, the reason why 4 bits of y (3) and y (7) are taken is 4 bits to set the number of input bits of the data coder to 8 bits. In the data coder 101-104, data inputted in parallel are converted and serialized. Since the original data amount is compressed to half of the 32 bits, the original data is compressed and output. When the signal is inversely converted, the original signal can be restored.

As described above, the present invention can be configured with simple logic by addition and subtraction, so that custom design is effective and real-time processing can be effectively used for a system requiring high speed. It is.

Claims (1)

A digital VTR or real-time image processing apparatus, comprising: an A / D converter 10 for converting an analog image signal into a digital signal in accordance with a sampling clock pulse, and a demultiplexer 20 for storing the image data in each latch circuit for calculation. And an adder and a subtractor 41-44 for adding and subtracting the latch circuit 31-38 and the output data of the latch circuit 31-38 in accordance with the presence or absence of an addition signal for performing the adama conversion algorithm. A latch circuit (51-58) for temporarily storing the added and subtracted data for the next operation, a multiplexer (61-64) for selectively outputting the output data of the latch circuit (51-58) in accordance with a control signal; An adder and a subtractor 71-73 for adding and subtracting the output data of the multiplexer 61-64 to perform a conversion algorithm, and decomposing and temporarily storing the added and subtracted data for proper coding. A multiplexer 80 and a latch circuit 91-98, and a data coder 101-104 for reducing the number of bits of the converted data output from the latch circuits 91-98, and correcting and coding the order. Adamal converter for data compression, characterized in that the high speed data compression is possible with a simple configuration.