KR930004303Y1 - Electronic circuit driver - Google Patents

Electronic circuit driver Download PDF

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Publication number
KR930004303Y1
KR930004303Y1 KR2019900002593U KR900002593U KR930004303Y1 KR 930004303 Y1 KR930004303 Y1 KR 930004303Y1 KR 2019900002593 U KR2019900002593 U KR 2019900002593U KR 900002593 U KR900002593 U KR 900002593U KR 930004303 Y1 KR930004303 Y1 KR 930004303Y1
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South Korea
Prior art keywords
circuit
pnp transistor
main circuit
base
transistor
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KR2019900002593U
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Korean (ko)
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KR910017454U (en
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공동수
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금성일렉트론 주식회사
문정환
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Priority to KR2019900002593U priority Critical patent/KR930004303Y1/en
Publication of KR910017454U publication Critical patent/KR910017454U/en
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Publication of KR930004303Y1 publication Critical patent/KR930004303Y1/en

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details

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  • Amplifiers (AREA)
  • Electronic Switches (AREA)

Abstract

내용 없음.No content.

Description

전자회로의 동작구동회로Operation drive circuit of electronic circuit

첨부한 도면은 본 고안 전자회로의 동작구동회로도.The accompanying drawings are operation driving circuit diagram of the electronic circuit of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 동작구동회로 12 : 바이어스회로11: operation driving circuit 12: bias circuit

13 : 주요회로 Q1,Q2 : 피엔피트랜지스터13: main circuit Q1, Q2: PNP transistor

Q3 : 전계효과트랜지스터(FET) I : 전류원Q3: Field Effect Transistor (FET) I: Current Source

본 고안은 전자회로의 동작구동회로에 관한 것으로, 특히 집적회로의 동작구동에 적당하도록 한 전자회로의 동작구동회로에 관한 것이다.The present invention relates to an operation driving circuit of an electronic circuit, and more particularly, to an operation driving circuit of an electronic circuit adapted to operate an integrated circuit.

일반적으로 집적회로등의 전자회로에서 동작구동을 위한 초기전원공급시 주요회로에 전원이 직접 인가되면, 주요회로각부에 순차적으로 공급되지 않아 순간적 과전류 또는 순간펄스등이 발생될 수 있어서 시스템의 동작불안이 발생된다. 이에따라 전원부분에 서어지(serge)회로 혹은 보호회로등 복잡하고 값비싼회로를 내장해야 한다.In general, if the power is directly applied to the main circuit during initial power supply for operation driving in electronic circuits such as integrated circuits, it is not supplied to each part of the main circuit sequentially, which may result in instantaneous overcurrent or instantaneous pulse, resulting in unstable operation of the system. Is generated. As a result, complex and expensive circuits such as surge or protection circuits must be built into the power supply.

본 고안은 이와같은 종래 문제점을 해소하고자 주요 회로의 동작을 위한 전원공급시 주요회로의 1차동작회로의 바이어스부터 순차적으로 인가되도록 하여 주요회로의 오동작 및 파괴를 방지할수 있도록 한 스타트-업(start-up)회로를 안출한 것으로, 이를 첨부한 도면을 참조해 상세히 설명하면 다음과 같다.In order to solve such a conventional problem, the present invention is applied to sequentially apply the bias of the primary operation circuit of the main circuit when the power is supplied for the operation of the main circuit so as to prevent malfunction and destruction of the main circuit. -up) to devise a circuit, it will be described in detail with reference to the accompanying drawings as follows.

첨부한 도면은 본 고안에 따른 전자회로의 동작구동 회로도로서 이에 도시한 바와같이 바이어스회로(12) 및 주요회로(13)에 공급되는 전원전압(Vcc)을 저항(R1)을 통해 에미터에 공급인가받는 피엔피트랜지스터(Q1),(Q2)가 콜렉터를 공통으로 전류원(I)에 연결하고, 상기 전원전압(Vcc)을 다이오드(D1-D3)를 통한 후 상기 피엔피트랜지스터(Q1)의 베이스 및 전계효과트랜지스(Q3)의 드레인에 연결하며, 상기 피엔피트랜지스터(Q2)의 베이스를 상기 바이어스회로(12) 및 주요회로(13)에 공통연결하여 동작구동회로(11)를 구성하였다.The accompanying drawings are an operation driving circuit diagram of the electronic circuit according to the present invention, and as shown therein, a power supply voltage Vcc supplied to the bias circuit 12 and the main circuit 13 is supplied to the emitter through the resistor R1. The applied PNP transistors Q1 and Q2 connect the collector to the current source I in common, and the power supply voltage Vcc is connected through the diodes D1 to D3 and then the base of the PNP transistor Q1. And a drain connected to the field effect transistor Q3, and a base of the PNP transistor Q2 is commonly connected to the bias circuit 12 and the main circuit 13 to form an operation driver circuit 11.

이와같이 구성한 본 고안의 작용 및 효과를 설명하면 다음과 같다.Referring to the operation and effects of the present invention configured as described above are as follows.

먼저, 전원전압(Vcc)공급시 바이어스회로(12) 및 주요회로(13)는 동작하지 않고 동작구동회로(11)가 동작한다.First, when the power supply voltage Vcc is supplied, the bias circuit 12 and the main circuit 13 do not operate, but the operation drive circuit 11 operates.

즉, 다이오드(D1-D3)를 통해 피엔피트랜지스터(Q1)의 베이스 및 전계효과트랜지스터(Q3)에 공급되는데, 피엔피트랜지스터(Q1)의 베이스 전압은 Vcc-3VBE=VBE가 된다. 이 피엔피트랜지스터(Q1)의 베이스전압이 결정되어 턴온되면 전류원(I)이 동작하게 되고, 이 전류원(I)의 동작에 의해 피엔피트랜지스터(Q2)가 턴온된다. 이 피엔피트랜지스터(Q2)의 턴온에 의해 바이어스회로(12)가 동작함과 아울러 주요회로(13)가 동작한다.That is, the diodes D1 through D3 are supplied to the base of the PNP transistor Q1 and the field effect transistor Q3, and the base voltage of the PNP transistor Q1 becomes Vcc-3V BE = V BE . When the base voltage of the PNP transistor Q1 is determined and turned on, the current source I is operated, and the PNP transistor Q2 is turned on by the operation of the current source I. The bias circuit 12 is operated by the turn-on of the PNP transistor Q2 and the main circuit 13 is operated.

이때, 주요회로(13)의 바이어스전압은 Vcc-R1I-VBE,Q2및 바이어스회로(12)로 결정된다. 주요회로(13)가 동작하면 피엔피트랜지스(Q1)은 턴오프되게 되는데 이는 피엔피트랜지스터(Q1)의 베이스전압보다 피엔피트랜지스(Q2)의 베이스전압을 낮게 설계(VBE,Q1〉VBE,Q2)함으로써 가능하다. 즉, 페인피트랜지스터(Q1),(Q2)가 모두 턴온되면 초기에 피엔피트랜지스터(Q2)의 베이스전위가 피엔피트랜지스터(Q1)의 베이스전압(VB,Q1)과 같다가 바이어스회로(12) 및 주요회로(13)가 동작하면 상기 피엔피트랜지스터(Q2)의 베이스 전위(VBE,Q2)가 상기 피엔피트랜지스터(Q1)의 베이스전위(VBE,Q1)보다 더 낮게(VBE,Q1〉VBE,Q2)된다. 그러면 전류는 피엔피트랜지스터(Q2)를 통해 거의 흐르게 되므로 피엔피트랜지스터(Q1)은 턴오프된다. 또한, 전압(Vcc)을 다이오드(D1)(D2)(D3)를 순차 통한 후 저항 대신 사용된 게이트 및 소오스를 접지시킨 전계효과트랜지스터(Q3)에 인가함으로써 전원전압(Vcc)의 변동시에 상기 전계효과트랜지스터(Q3)에 흐르는 전류변화를 극소화시킬 수 있으며, 저할(R1)은 상기 피엔프랜지스터(Q1),(Q2)에 최적전류가 흐르게 하도록 설계하고, 피엔피트로랜지스터(Q2)의 베이스전압을 안정화시키기 위해 바이어스 회로(12)에는 열에 대한 고안정회로로 설계하여 주요회로(13)를 열적으로 보안하면서 스타트-업시킬수 있는 회로로 작용한다.At this time, the bias voltage of the main circuit 13 is determined by Vcc-R1I-V BE , Q2 and the bias circuit 12. When the main circuit 13 operates, the PNP transistor Q1 is turned off, which is designed to make the base voltage of the PNP transistor Q2 lower than the base voltage of the PNP transistor Q1 (V BE , Q1 ). V BE , Q2 ). That is, the painter P transistor (Q1), (Q2) that is the base potential of the P & P transistor (Q2) initially equal to the blood base voltage (V B, Q1) of the & P transistor (Q1) a bias circuit (12 when both turn-on ) And the main circuit 13, the base potential (V BE , Q2 ) of the PNP transistor Q2 is lower than the base potential (V BE , Q1 ) of the PNP transistor Q1 (V BE , Q1 > V BE , Q2 ). Then, the current flows almost through the PNP transistor Q2, so the PNP transistor Q1 is turned off. In addition, the voltage Vcc is sequentially applied through the diodes D1, D2, and D3, and then applied to the field effect transistor Q3 in which the gate and source used in place of the resistor are grounded, thereby changing the power supply voltage Vcc. The current change flowing through the field effect transistor Q3 can be minimized, and the lower limit R1 is designed to allow the optimal current to flow through the P and C transistors Q1 and Q2. In order to stabilize the base voltage, the bias circuit 12 serves as a circuit capable of starting-up while thermally securing the main circuit 13 by designing a high-stable circuit for heat.

이와같이 본 고안은 주요회로(13)를 동작구동시키기 위해 간단한 회로로 구성되며, 동작구동회로의 전류를 최소로 설계함으로써 전력손실이 낮고, 전계효과트랜지스터(Q3)사용하여 전원전압의 변화에 따른 그의 소오스-드레인간 전류변화를 극소화하도록 게이트-소오스를 쇼트시켜 설계하였다.In this way, the present invention is composed of a simple circuit for driving the main circuit 13, the power loss is low by designing the current of the operation driving circuit to a minimum, and using the field effect transistor (Q3) according to the change of the power supply voltage The gate-source was designed to minimize the source-drain current change.

이상에서 설명한 바와같이 본 고안은 간단한 회로 구성으로 주요회로의 동작구동회로를 구성하고, 그 동작 구동회로의 전류를 최소화하도록 설계하였으며, 전원전압(Vcc)공급시 주요회로의 1차동작회로 바이어스부터 순차로 인가됨으로써 주요회로의 오동작 및 파괴를 방지할수 있어서, 본 고안 회로를 내장한 시스템의 수명 및 신뢰도를 향상시킬수 있는 효과가 있다.As described above, the present invention is designed to configure the operation driver circuit of the main circuit with a simple circuit configuration, and to minimize the current of the operation driver circuit, starting from the primary operation circuit bias of the main circuit when supplying the power voltage (Vcc). By applying sequentially, it is possible to prevent the malfunction and destruction of the main circuit, there is an effect that can improve the life and reliability of the system incorporating the circuit of the present invention.

Claims (1)

주요회로(13) 및 바이어스회로(12)에 공급되는 전원전압(Vcc)을 저항(R1)을 통해 에미터에 공통 인가받는 피엔피트랜지스터(Q1),(Q2)의 콜렉터를 전류원(I)에 공통접속하고, 상기 전원전압(Vcc)을 다이오드(D1-D3)를 통해서 상기 피엔피트랜지스터(Q1)의 베이스에 접속함과 아울러 소오스가 접지된 전계효과트랜지스터(Q3)의 드레인에 접속하며, 상기 피엔피트랜지스터(Q2)의 베이스를 상기 바이어스회로(12) 및 주요회로(13)에 연결하여 구성한 것을 특징으로 하는 전자회로의 동작구동회로.The collectors of the PNP transistors Q1 and Q2, which are commonly applied to the emitter via the resistor R1, with the power supply voltage Vcc supplied to the main circuit 13 and the bias circuit 12 to the current source I. Common connection, the power supply voltage Vcc is connected to the base of the PNP transistor Q1 through diodes D1-D3, and the source is connected to the drain of the field effect transistor Q3 grounded; An operation circuit for an electronic circuit, comprising: a base of a PNP transistor (Q2) connected to the bias circuit (12) and a main circuit (13).
KR2019900002593U 1990-03-06 1990-03-06 Electronic circuit driver KR930004303Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900002593U KR930004303Y1 (en) 1990-03-06 1990-03-06 Electronic circuit driver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019900002593U KR930004303Y1 (en) 1990-03-06 1990-03-06 Electronic circuit driver

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Publication Number Publication Date
KR910017454U KR910017454U (en) 1991-10-28
KR930004303Y1 true KR930004303Y1 (en) 1993-07-10

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KR2019900002593U KR930004303Y1 (en) 1990-03-06 1990-03-06 Electronic circuit driver

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KR910017454U (en) 1991-10-28

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