KR930004260B1 - N-bit digital pulse generator using personal computer - Google Patents

Abstract

The programmable digital pulse generator equipped in a personal computer generates multi-channel digital pulses. The digital pulse generator includes a memory unit (21) for storing n- bit pattern data transmitted from a personal computer on a first and a second area sequentially, a clock signal input unit (23) for regulating output speed of n-bit pattern data according to control signal transmitted from a personal computer and clock signal, an address signal generator (24) for designating address of the memory unit (21) to read out pattern data, a control signal generator (26) for generating read enable signal to read out pattern data by channel units, and a data a buffer (27) for latching channel data and for transmitting the channel data by word units.

Description

N-bit digital pulse generator using personal computer

1 is a block diagram schematically showing a digital pulse generator according to the present invention associated with a personal computer.

FIG. 2 is a block diagram showing in detail the signal processor shown in FIG.

* Explanation of symbols for main parts of the drawings

10: Personal Computer 21: Dual Port RAM

23: external clock input unit 24: address generator

25: channel select signal generator 29: interrupt generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator, and more particularly, to a digital waveform data generator for outputting any particular waveform by a user using a personal computer.

Conventional waveform generators are analog waveform generators, and in order to obtain digital data on arbitrary waveforms, it is possible to use a separate analog-to-digital converter (A-D converter). In this case, there are many difficulties in obtaining desired digital data due to external noise, etc., and there is also a hassle of configuring a separate circuit.

In addition, the conventional waveform generator is a one-channel waveform generator, or a device for generating a constant and continuous frequency within a predetermined frequency band. Thus, it is impossible to process a large amount of frequencies and it is impossible to use to process discrete signals that are not continuous.

It is an object of the present invention to provide a program function digital pulse generator which can be simply used in the form of internal mounting of a personal computer and can be provided to a plurality of external input channels instead of having a separate device form as a conventional measuring instrument.

The present invention for this purpose generally comprises a memory means for storing data for a desired waveform in a personal computer, and a clock input and address generator for accessing the data stored in the memory means by an external clock and varying the speed. And an interrupt generator for updating successive new next data into said memory means.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of one embodiment of a digital pulse generator according to the present invention.

Since the personal computer 10 is a general computer and the signal processing device 20 is inserted as one peripheral device, the personal computer 10 assigns a new address to the signal processing device 20 or avoids address duplication with other boards. Should be set.

The personal computer 10 generates digital values of waveforms designated by a user by a program. This digital signal is signal-processed by the signal processing unit 20 and then supplied to the necessary device through the data output unit 30.

Numeral 40 is a means for varying the generation speed of the digital waveform output from the personal computer.

Referring to FIG. 2, a more detailed configuration of the present invention is shown.

As shown in the left part of the figure, the apparatus may be arranged in an internal expansion slot of a personal computer, thus making common use of the computer's control bus, data bus and address bus.

First, the user selects a signal of a desired waveform by using the personal computer 10 and converts it into a digital signal of n bits by a program. When various waveforms are provided, they are converted to n bits as well. The converted digital data is loaded onto the data bus in a usual manner and then combined with a control signal generator 3 for writing and reading data, and an address selection circuit 7 and an address buffer 9 to provide a data buffer ( It is input to the memory means 21 via 5).

The memory means 21 comprises a dual port RAM in which both an address bus and a data bus are connected to both ports. Therefore, it has the capability of inputting data from the computer 10 through the address bus and data bus of one port for input and outputting the stored waveform data through the address and data port of the other port for output. In the memory means 21, data is stored one word of m bits per channel.

The dual port RAM 21 is divided into an upper region and a lower region according to the present invention. This is because the data in the dual port RAM 21 must be inputted channel by channel and output channel by channel in accordance with the present invention when the external device requiring digital data has a plurality of input channels, thereby selectively specifying two areas during data output. The purpose is to keep updating new data.

Since the address decoder 22 can insert the n-bit data generator of the present invention as one package into the expansion slot of the computer, it treats a unique address in order to treat it as one peripheral as described above. It is for designation.

The external clock input unit 23 receives the external clock and divides it so that the digital data generation rate output from the dual port RAM 21 can be varied. In addition, the address generator 24 sequentially accesses the address of the dual port RAM 21 according to the clock signal generated from the clock input unit 23. The data to be accessed can be output to the outside by enabling the control signal generator 26 by a certain control signal from the clock input unit 23.

When the accessed data of the region on the dual port RAM 21 is output through the data buffer 27, the interrupt generator 29 generates an interrupt signal INT a to the personal computer 10, and the data of the lower region is output. Generates an interrupt signal INT b. This interrupt signal is a signal that causes the CPU (not shown) of the personal computer 10 to input new digital data for any desired waveform, and the INT a signal reads the last address of the upper region of the two regions of the dual port RAM. An INT b signal is generated at the time of reading the last address of the lower area of this RAM to update both areas with new data.

The output digital data is input to the line driver and the impedance matching unit 28 via the data buffer 27, where the impedance is matched and then output.

The channel select signal generator 25 is a means for sequentially selecting m channels of a plurality of external devices that require digital waveforms generated by the n-bit digital waveform generator of the present invention. The channel select signal generator 25 decodes the address of the address generator 24 to sequentially select a plurality of input channels of an external device so that corresponding data is input through the data output unit 30. Do it.

Data output for each channel according to the present invention is shown in FIG. It can be seen that the accessed n-bit data is output for every m channels, so that even if the channel is expanded, it can be provided as an input of multiple channels according to the present invention.

Claims (3)

A n-bit pulse generator for inputting digital data required for a plurality of input channels, the n-bit for each of a plurality of channels converted for each of a plurality of waveforms required for the plurality of input channels through a data bus of a personal computer. Memory means 21 for sequentially storing bit pattern data in a memory area divided into a first area and a second area under control of an address and a control signal of a personal computer; A clock input section (23) for dividing a clock generated under the control of a personal computer to adjust the output speed of data stored in the memory means; An address generator 24 which sequentially specifies the addresses of the first and second regions of the memory means 21 in which the plurality of respective n-bit data are stored in accordance with a clock signal from the clock input section 23; Wow; A control signal generator (26) for enabling read-out of data for each channel in the sequentially accessed memory means (21) according to the clock signal from the clock input section (23); An n-bit digital pulse data generator using a personal computer including a data buffer (27) for temporarily latching the output data and outputting one word for each external channel. 2. The method according to claim 1, wherein when the last data in the first area of the memory means 21 is output in accordance with the signal generated from the address generator 24, and in the second area of the memory means 21. And an interrupt generator (29) for generating an interrupter to a computer when the last data of the output is output so that a plurality of new n-bit data are sequentially stored in the area, respectively. The channel selection method of claim 1 or 2, wherein the data output from the data buffer 27 by one word for each channel is distributed to a corresponding external channel according to the output address signal of the address generator 24. An n-bit digital data generator using a personal computer further comprising a signal generator (25).