KR930004124B1 - Device isolation method of i.c. - Google Patents

Device isolation method of i.c. Download PDF

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KR930004124B1
KR930004124B1 KR1019900010608A KR900010608A KR930004124B1 KR 930004124 B1 KR930004124 B1 KR 930004124B1 KR 1019900010608 A KR1019900010608 A KR 1019900010608A KR 900010608 A KR900010608 A KR 900010608A KR 930004124 B1 KR930004124 B1 KR 930004124B1
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polycrystalline silicon
film
pad
window
oxide film
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KR1019900010608A
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Korean (ko)
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KR920003460A (en
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전영권
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/784—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

The method for isolating a device comprises (a) forming a pad oxide film (1) of 500 angstroms or less on the silicon substrate (10), (b) depositing a polycrystalline silicon (2) of 3000 angstroms or less, (c) masking a window-forming part and then lifting off the silicon, (d) depositing a nitride film (3) of 3000 angstroms and then covering SOG on the film (3) to flatten it, (e) dry-etching the film (4) to expose the silicon (2) on the window, (f) implanting a channel stop ion (5) into the silicon-exposed window, (g) forming a field oxide film (9), and (h) etching an oxidized mask to form a device-isolating region.

Description

반도체 집적회로의 소자 분리방법Device Separation Method of Semiconductor Integrated Circuits

제1(a)도∼제1(c)도는 종래의 소자 분리 방법 공정도.1 (a) to 1 (c) are process steps of a conventional device isolation method.

제2(a)도∼제2(f)도는 본 발명에 따른 소자 분리 방법 공정도.2 (a) to 2 (f) are process diagrams of a device separation method according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 산화막 2 : 다결정 실리콘1: oxide film 2: polycrystalline silicon

3 : 질화막 4 : 포토 레지스트3: nitride film 4: photoresist

5 : 채널 스톱 이온 6 : SOG5: channel stop ion 6: SOG

7 : 절연막 8 : 금속 배선7: insulating film 8: metal wiring

9 : 필드 산화막 10 : 실리콘 기판9: field oxide film 10: silicon substrate

본 발명은 반도체 집적회로의 소자 분리방법에 관한 것으로 다결정 Si과 산화막의 적층 패드를 이용하여 필드 산화막의 두께를 증가시키고 버드빅(Bird's Beak)을 감소시킬 수 있도록하여 고집적 소자의 미세 분리가 가능하도록한 반도체 집적회로의 소자 분리 방법에 관한 것이다.The present invention relates to a device isolation method of a semiconductor integrated circuit to increase the thickness of the field oxide film and reduce the Bird's Beak by using a multilayer pad of polycrystalline Si and oxide to enable fine separation of highly integrated devices. A device isolation method of a semiconductor integrated circuit.

종래에는 다결정 실리콘을 버퍼층으로 이용하여 패드 산화막 두께를 얇게하고 질화막을 두껍게 형성한 산화마스크를 이용하여 버드빅을 감소시키도록 하는 PBL(Poly Buffered Locos)방법이 있었다.Conventionally, there has been a PBL (Poly Buffered Locos) method using polycrystalline silicon as a buffer layer to reduce the Budvik using an oxide mask having a thin pad oxide film and a thick nitride film.

즉 제1(a)도에서와 같이 Si 기판(10)에 산화막(1)과 다결정 실리콘(2) 및 질화막(3)으로 형성된 산화마스크층을 형성하고, 제1(b)도에서와 같이 포토레지스트(4)를 이용하여 윈도우(Window)를 형성하고 채널 스톱 이온(5)을 주입하고 제1(c)도에 도시된 바와같이 필드 산화막(9)을 형성한다.That is, as shown in FIG. 1 (a), an oxide mask layer formed of the oxide film 1, the polycrystalline silicon 2, and the nitride film 3 is formed on the Si substrate 10, and as shown in FIG. 1 (b). Using the resist 4, a window is formed, the channel stop ions 5 are implanted, and the field oxide film 9 is formed as shown in Fig. 1 (c).

그러나 이와같은 종래의 방법에 있어서는 필드산화를 할때 산화마스크의 윈도우를 모서리를 따라 다결정 실리콘의 일부가 산화막을 형성하므로 산화마사크를 식각 제거할때 다결정 실리콘의 두께가 불균일 하게되고, 소자 분리폭이 미세하여 짐에 따라 응력 및 면적 효과에 따른 소자분리 산화막 두께의 감소로 필드산화막의 쓰레시홀드(threshold)전압이 저하되는 문제점이 있었다.However, in the conventional method, since the portion of the polycrystalline silicon forms an oxide film along the edge of the window of the oxide mask during field oxidation, the thickness of the polycrystalline silicon becomes uneven when the oxide mask is etched away. As the microstructure becomes smaller, there is a problem in that the threshold voltage of the field oxide film is lowered due to a decrease in the thickness of the device isolation oxide film due to stress and area effects.

이에 따라 본 발명은 상기한 문제점을 제거하기 위한 것으로서 제2(a)도에 도시된 바와같이 실리콘 기판(10)위에 500Å이하의 패드산호막(1)을 형성하고 3000Å이하의 다결정 실리콘(2)을 증착한후 윈도우가 형성될 부분에 다결정 실리콘(2)이 남도록 프토레지스트로 마스크 한후에 그 부분외의 다결정 실리콘을 식각 제거한다.Accordingly, the present invention is to eliminate the above problems, as shown in FIG. 2 (a), the pad coral film 1 of 500 mW or less is formed on the silicon substrate 10, and the polycrystalline silicon 2 of 3000 m or less is formed. After deposition, the mask is masked with a photoresist such that the polycrystalline silicon 2 remains in the portion where the window is to be formed, and then the polycrystalline silicon other than the portion is etched away.

이후 제2(b)도에서와 같이 질화막(3)을 3000Å이하의 두께로 증착하고 제2(c)도와 같이 SOG(6)(이때 SOG대신에 포토레지스트를 사용하여도 된다)를 도포하여 평탄화 시킨다음 제2(d)도와 같이 질화막(3)을 증착 두께 이상으로 건식 식각하여 윈도우에 다결정 실리콘(2)이 드러나도록 하고, 채널스톤 이온(5)을 주입한다.Thereafter, as shown in FIG. 2 (b), the nitride film 3 is deposited to a thickness of 3000 GPa or less, and as shown in FIG. 2 (c), the SOG 6 (in this case, a photoresist may be used instead of SOG) is planarized. Then, as shown in FIG. 2 (d), the nitride film 3 is dry-etched to a thickness greater than the deposition thickness so that the polycrystalline silicon 2 is exposed in the window, and the channel stone ions 5 are implanted.

이후 제2(e)도와 같이 산화성 분위기에서 열처리하여 필드 산화막(9)을 형성하고, 제2(f)도와 같이 산화마스크를 식각 제거하여 소자분리 영역을 형성한후 MOS트랜지스터를 형성한다.Then, as shown in FIG. 2 (e), the field oxide film 9 is formed by annealing in an oxidizing atmosphere. As shown in FIG.

여기서 미설명부호 7은 절연막이고, 8은 금속배선이다. 따라서 본 발명에 따른 반도체 집적회로의 소자분리 방법은 다결정 실리콘과 산화막의 이중패드를 통하여 산화를 시킴으로서 미세소자 분리 폭에서도 필드산화막의 두께를 증가시킬 수 있으며 다결정 실리콘의 희생산화를 통하여 버드빅을 감소시킬 수 있으므로 소자의 집적화가 가능한 효과를 갖는다.Reference numeral 7 is an insulating film, and 8 is a metal wiring. Therefore, the device isolation method of the semiconductor integrated circuit according to the present invention can increase the thickness of the field oxide film even in the micro device isolation width by oxidizing through the double pad of the polycrystalline silicon and the oxide film, and reduces Budvik through sacrificial oxidation of the polycrystalline silicon. Since it can be made, the integration of the device is possible.

Claims (3)

질화막과 패드 산화막의 윈도우에 다결정 실리콘의 패드를 형성하여 다결정 실리콘과 산화박막이 적층 구조로된 패드를 통하여 산화성 분위기에서 열처리하여 필드 산화막을 형성한 후 산화 마스크를 식각 제거하는 반도체 집적회로의 소자 분리방법.Isolation of a device in a semiconductor integrated circuit in which a pad of polycrystalline silicon is formed on a window of a nitride film and a pad oxide film, and a field oxide film is formed by heat treatment in an oxidative atmosphere through a pad having a stacked structure of polycrystalline silicon and an oxide thin film, followed by etching of an oxide mask. Way. 제1항에 있어서, 다결정 실리콘 패드를 형성하는 방법으로서 패드산화막을 형성한 다음 다결정 실리콘을 증착하고 윈도우가 형성될 부분을 마스크한 후에 그 부분외의 다결정 실리콘을 식각 제거한 다음 질화막을 3000Å이하의 두께로 증착하고 SOG나 포토레지스트를 도포하여 평탄화시킨후 질화막을 증착 두께 이상으로 건식식각하여 윈도우에 다결정 실리콘의 표면이 나타나도록 한 것을 특징으로 하는 반도체 집적 회로의 소자 분리방법.The method of forming a polycrystalline silicon pad according to claim 1, further comprising forming a pad oxide film, depositing polycrystalline silicon, masking a portion where a window is to be formed, and etching away the polycrystalline silicon other than the portion, and then removing the nitride film to a thickness of 3000 Å or less. And depositing a planarized film by applying SOG or photoresist, and then etching the nitride film to a thickness greater than or equal to the deposition thickness so that the surface of the polycrystalline silicon appears on the window. 제1항에 있어서, 다결정 실리콘 패드는 도핑된 다결정 실리콘으로 함을 특징으로 하는 반도체 집적회로의 소자 분리방법.The method of claim 1, wherein the polycrystalline silicon pad is made of doped polycrystalline silicon.
KR1019900010608A 1990-07-13 1990-07-13 Device isolation method of i.c. KR930004124B1 (en)

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