KR930003323A - Semiconductor device device isolation method and semiconductor device having device isolation region - Google Patents

Semiconductor device device isolation method and semiconductor device having device isolation region Download PDF

Info

Publication number
KR930003323A
KR930003323A KR1019910013226A KR910013226A KR930003323A KR 930003323 A KR930003323 A KR 930003323A KR 1019910013226 A KR1019910013226 A KR 1019910013226A KR 910013226 A KR910013226 A KR 910013226A KR 930003323 A KR930003323 A KR 930003323A
Authority
KR
South Korea
Prior art keywords
layer
dps
spacer
forming
substrate
Prior art date
Application number
KR1019910013226A
Other languages
Korean (ko)
Other versions
KR940001813B1 (en
Inventor
김윤기
김병렬
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910013226A priority Critical patent/KR940001813B1/en
Publication of KR930003323A publication Critical patent/KR930003323A/en
Application granted granted Critical
Publication of KR940001813B1 publication Critical patent/KR940001813B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Abstract

내용 없음.No content.

Description

반도체 장치 소자 분리방법 및 그 소자 분리 영역을 갖는 반도체 장치Semiconductor device device isolation method and semiconductor device having device isolation region

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 소자 분리 방법을 설명하는 공정 수순도,2 is a process flowchart illustrating the device isolation method of the present invention,

제3도는 본 발명의 적용예를 보인 트렌치 구조를 갖는 반도체 장치의 단면도이다.3 is a cross-sectional view of a semiconductor device having a trench structure showing an application example of the present invention.

Claims (6)

반도체 장치의 소자 분리 방법에 있어서, 반도체 기판 상에 절연층을 형성하여 소자 분리 영역의 정의를 위한 개구부 형성 단계; 이 개구부내에 제1스페이서 형성 및 개구부 내에 제1스페이서로 한정된 영역에 기판이 노출되는 단계; 상기 개구부 내의 스페이서로 한정된 영역상에 기판과 동일 도전층의 불순물이 함유되는 폴리실리콘층(DPS충)을 형성시키는 단계; 개구부내에 형성된 DPS층의 불순물이 기판으로 확산되어 채널 저지층을 형성하도록 열공정을 실시하는 단계; 상기 절연층을 제거하고 산화층을 침전하여 제1의 스페이서와 접한 제2의 스페이서를 형성하여 DPS층을 사이에 두고 서로 이격 배치된 스페이서(S)를 형성하는 단계, 상기 스페이터(S) 형성시 노출된 DPS층을 포함하여 기판 전면에 걸쳐 열산화막을 성장시켜 소자 분리 영역을 형성하는 단계로 이루어짐을 특징으로 하는 반도체 소자 분리 방법.An element isolation method of a semiconductor device, comprising: forming an insulating layer on a semiconductor substrate to form an opening for defining an element isolation region; Forming a first spacer in the opening and exposing the substrate to a region defined by the first spacer in the opening; Forming a polysilicon layer (DPS) containing impurities of the same conductive layer as the substrate on a region defined by the spacers in the opening; Performing a thermal process to diffuse impurities in the DPS layer formed in the openings into the substrate to form a channel blocking layer; Removing the insulating layer and precipitating an oxide layer to form a second spacer in contact with the first spacer to form spacers S spaced apart from each other with a DPS layer interposed therebetween; Forming a device isolation region by growing a thermal oxide film over the entire surface of the substrate including the exposed DPS layer. 제1항에 있어서, 상기한 제2의 스페이서 형성을 위한 산화층 형성은 저압 화학 기상 증착 방법으로 침적 형성됨을 특징으로 하는 반도체 소자 분리 방법.The method of claim 1, wherein the oxide layer for forming the second spacer is deposited by low pressure chemical vapor deposition. 제1항에 있어서, 확산에 의해 형성된 채널 저지층을 활성 영역과는 적어도 스페이서(S)의 폭만큼 이격되어 형성되므로서 채널 저지층의 불순물이 활성 영역으로 침투를 저지하도록 형성됨을 특징으로 하는 반도체 소자 분리 방법.The semiconductor of claim 1, wherein the channel blocking layer formed by diffusion is formed to be spaced apart from the active region by at least the width of the spacer S, and the impurities of the channel blocking layer are formed to prevent penetration into the active region. Device isolation method. 소자 분리 영역을 갖는 반도체 장치에 있어서, 소자 분리 영역은 대략 반원 형태의 단면을 갖는 스페이서 또는 절연층(S)이 불순물 함유 폴리실리콘(DPS)층(19)을 사이에 두고 기판상에 수평 방향으로 이격 배치된 상기 한쌍의 절연층(S)과 이위에 형성딘 열산화층과, 상기 DPS층 밑에 형성된 채널스톱층(21)을 포함하여 형성된 소자 분리 영역을 갖는 것이 특징린 반도체 장치.In a semiconductor device having an element isolation region, the element isolation region is formed in a horizontal direction on a substrate with a spacer or insulating layer S having an approximately semicircular cross section interposed therebetween with an impurity-containing polysilicon (DPS) layer 19 interposed therebetween. And a device isolation region including a pair of insulating layers (S) spaced apart from each other, a thermal oxidation layer formed thereon, and a channel stop layer (21) formed under the DPS layer. 제4항에 있어서, 상기 채널저지층(21)은 활성영역과는 적어도 절연충(S)의 폭만큼 이격되어 형성된 것을 특징으로 하는 소자분리영역을 갖는 반도체 장치.5. The semiconductor device according to claim 4, wherein the channel blocking layer (21) is formed spaced apart from the active region by at least the width of the insulating insect (S). 트렌치 구조를 갖는 반도체 장치의 소자 분리 방법에 있어서, 트렌치 내의 내부면 상에 형성되는 블순층의 형성은 트렌치 홀 형성후, 트렌치 내에는 불순물 함유된 폴리실리콘층(DPS)을 침적 형성하고, 열공정을 실시하여 침적된 DPS층의 불순물이 기판으로 확산되도록 하여 불순물층을 형성하도록 하는 것을 특징으로 하는 소자분리영역을 갖는 반도체 장치.In the device isolation method of a semiconductor device having a trench structure, the formation of the pure layer formed on the inner surface of the trench is followed by the formation of the trench holes, followed by depositing and forming a polysilicon layer (DPS) containing impurities in the trench, And forming an impurity layer by allowing impurities in the deposited DPS layer to diffuse into the substrate to form an impurity layer. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910013226A 1991-07-31 1991-07-31 Isolation method and device of semiconductor KR940001813B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910013226A KR940001813B1 (en) 1991-07-31 1991-07-31 Isolation method and device of semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910013226A KR940001813B1 (en) 1991-07-31 1991-07-31 Isolation method and device of semiconductor

Publications (2)

Publication Number Publication Date
KR930003323A true KR930003323A (en) 1993-02-24
KR940001813B1 KR940001813B1 (en) 1994-03-09

Family

ID=19318081

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910013226A KR940001813B1 (en) 1991-07-31 1991-07-31 Isolation method and device of semiconductor

Country Status (1)

Country Link
KR (1) KR940001813B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023163498A1 (en) * 2022-02-24 2023-08-31 주식회사 리그넘 Method for preparing scratch-resistant bio-additive for addition to plastics, and scratch-resistant bio-additive for addition to plastics prepared thereby

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023163498A1 (en) * 2022-02-24 2023-08-31 주식회사 리그넘 Method for preparing scratch-resistant bio-additive for addition to plastics, and scratch-resistant bio-additive for addition to plastics prepared thereby

Also Published As

Publication number Publication date
KR940001813B1 (en) 1994-03-09

Similar Documents

Publication Publication Date Title
KR920018977A (en) Semiconductor device and integrated circuit and manufacturing method thereof
KR940006248A (en) Semiconductor device and manufacturing method
KR920001754A (en) Method for manufacturing a multilayer gate electrode for MOS transistors
JPH10189587A (en) Composite dielectric layer and forming method thereof
KR930009016B1 (en) Wiring contact structure of semiconductor device and manufacturing method
KR890012362A (en) Manufacturing method of semiconductor device
KR970008500A (en) Polycrystalline Silicon Thin Film Transistor and Manufacturing Method Thereof
KR970024305A (en) Method of manufacturing thin film transistor substrate for liquid crystal display device
KR920013606A (en) Self-aligned gate device manufacturing method using heat resistant double layer
KR930003323A (en) Semiconductor device device isolation method and semiconductor device having device isolation region
US3810795A (en) Method for making self-aligning structure for charge-coupled and bucket brigade devices
KR880005690A (en) BiCMOS manufacturing method using selective epitaxial layer
KR970030676A (en) Semiconductor device and manufacturing method thereof
KR920005296A (en) Semiconductor Device Separation Manufacturing Method
KR950001900A (en) New electrode structure formation method using amorphous silicon and polycrystalline silicon
KR920015539A (en) Single poly ypyrom cells and manufacturing method
JPH01260857A (en) Semiconductor device and manufacture thereof
JPH01200672A (en) Coplanar transistor and manufacture thereof
KR930001452A (en) Trench source / drain MOSFET and manufacturing method
KR960026958A (en) Transistor with thin junction and method of manufacturing same
KR920022555A (en) Manufacturing Method of Semiconductor Device
KR920015619A (en) Manufacturing method of elevated source / drain MOS FET
JPS6276562A (en) Semiconductor device and manufacture thereof
KR930001439A (en) Manufacturing Method of Semiconductor Device
KR960026427A (en) Method of manufacturing thin film transistor

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010215

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee