KR930002191B1 - Method of signalling common channel - Google Patents

Abstract

The signalling terminal board provides message transfer functions to TDX-1 family to construct inter-network protocol using common line signalling method. The borad includes a bus error detector (14) for monitoring operating state of an MPU to reconstruct exchange system when abnormal operation of an MPU occurs, an interrupt controller (18) for detecting interrupts generated during transmission and reception process, register (23) for inspecting operating state of units in the terminal board, a state control register (24) for controlling operating state of the terminal board, and a DLC interfacing controller (25) for providing a trunk module function to the terminal board and for exchanging signal network message between exchange stations.

Description

Signal terminal board for implementing level 1 and 2 functions of common line signaling (CCS No. 7) message transfer unit (MTP)

1 is an overall configuration diagram of a message delivery unit to which the present invention is applied;

2 is a functional block diagram of a signal terminal board according to the present invention,

(A) and (b) of FIG. 3 are detailed configuration diagrams of an interrupt control unit,

4 is a detailed configuration diagram of a DLC access controller;

5 is a detailed configuration diagram of the signal loop control unit;

6 is a detailed configuration diagram of the bus error recognition and generation unit.

* Explanation of symbols for main parts of the drawings

11: microprocessor 12: programmable ROM

13: static RAM 14: bus error recognition and generation unit

15 clock generation and division unit 16 reset circuit

17: address decoder 18: interrupt control unit

19: DMA controller 20: serial communication controller

21: signal loop control unit 22: MFP

23: status recognition register 24: status control register

25: DLC access control unit 31: priority encoder

32: decoder 33: NAND gate

34: AND gate 40a-40d: input and output buffer

41: channel counter 42: control signal generator

43: DIP switch 44: channel comparator

45,48: serial / parallel exchanger 46,50: parallel / serial converter

47: DUSCC 49: Latch

61: OR gate 62: AND gate

63: Multi Vibrator

The present invention relates to a signaling terminal board in charge of a signal data link and a signal link function of a message transfer part (MTP) function of a common line signaling method (CCS No. 7).

Integrate various services to realize a comprehensive information communication network that will play the most important role in the future information society. It is in the stage of research and development.

An object of the present invention is to implement a manganese protocol by the common line signaling method by adding a message delivery function to the TDX-1 ("registered trademark"), a domestic electronic switch system that is already installed and operated at the main point as described above. In order to secure the base technology, and to provide the conditions to provide various services using the same, as well as the independence of the communication technology for the common line signaling method, a signal terminal board in charge of the signal data link and signal link functions is provided. In providing.

In order to achieve the above object, the present invention analyzes the message input through the STG bus in the message transfer unit of the electronic switchboard, and performs the control function of the signal terminal state for the internal signal message between level 3 and level 2. The message transfer to the side level 3 module is a signal terminal board that transmits through the STG bus using a specific channel of DLC, which is a trunk module, and accesses the MPU and the internal bus through the internal bus. Programmable ROM connected, static RAM connected to the internal bus, the MPU connected to the MPU, monitors the operation status of the MPU, recognizes the bus error due to the operation error of the control software, and informs the MPU to return the system to normal. Bus error recognition and generating means to recover, and operation synchronization of each device on board when power is supplied and reset is requested. Reset circuit means for maintaining, clock generation and distributing means for supplying a clock signal to each device on the board, and an address decoupling signal connected to the internal bus to generate a selection signal for the MPU to control each element on the board. Interlock control means connected to the internal bus to recognize an interrupt for processing a message transmission / reception process, and to perform an interrupt response cycle, a DMA control means connected to the internal bus, the internal bus and a DMA control means Serial communication control means (DSUCC), which is connected between the serial communication control means and the STG-bus, which has an independent message transmission / reception function, blocks the signal transmitted from the outside to the outside, and loops back the inside. Signal loop control means having a function of controlling the A status acknowledgment register connected to the sub-bus and the MFP to check the operation state in the board; a status control register connected to the internal bus and the MFP to control the operation state in the board to an appropriate state; and the signal loop control means, the MFP, and the state. It is characterized in that it is connected to the acknowledgment register and the status control register to provide a connection function to the trunk module, and comprises DLC access control means for exchanging signal network messages with message transfer units of other switching stations.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, the role of the present invention in the overall configuration of the message delivery unit will be described with reference to FIG. 1, and the function of the signal terminal board will be described with reference to FIG. Signal terminal board interprets the message coming from STG bus and performs the control function of signal terminal status for internal signal message between level 3 and level 2, and message to be transmitted to status level 3 module (MSU-Message Signal Unit) Is a trunk module of the TDX-1 series exchange, which is a DLC (Data Link Concetrator), which transmits using a specific channel (64Kbps) of 2.08Mbps. Messages received at the DLC are sent to the level 3 module via the STG bus in the signaling link function of the signaling terminal.

Looking at the functional block configuration of the signal terminal board through Figure 2 as follows.

In the figure, 11 is a microprocessor (hereinafter simply referred to as 'MPU'), 12 is a programmable ROM (hereinafter simply referred to as 'PROM'), 13 is a static RAM (hereinafter simply referred to as 'SRAM'), 14 is a bus error recognition and Generation section 15 is a clock generation and division section, 16 is a reset circuit, 17 is an address decoder, 18 is an interrupt control section, 19 is a DMA (Direct Memory Access) controller (hereinafter simply referred to as 'DMAC'), 20 is two channels The multi-function serial communication controller (hereinafter, simply referred to as 'DUSCC'), 21 denotes a signal loop controller, 22 denotes an MFP, 23 denotes a state recognition register, 24 denotes a state control register, and 25 denotes a DLC (Data Link Concetrator) connection controller.

The MPU 11 accesses and controls the devices in the board through the internal bus. In the embodiment of the present invention, the MC68000 is used.

The PROM 12 is a programmable ROM connected to the internal bus. In the embodiment of the present invention, two 32K bytes of EPROM (150 ns) are used.

The SRAM 13 is a static RAM connected to the internal bus. In the embodiment of the present invention, two SRAMs (120 ns) of 32K bytes are used.

The bus error recognition and generation unit 14 is connected to the staggered MPU 11, and recognizes the bus error about the memory access outside the memory area of each device on the board due to an operation error of the control software, and informs the MPU of this. It is to recover the system normally for a serious operation error in case of emergency, and monitors the operation state of the MPU 11 to initialize the control routine in which the above error occurs when the operation is stopped for a predetermined time.

The reset circuit section 16 simultaneously transmits the reset signal by the reset switch to each device in the board of the present invention when power is supplied and maintains the synchronization in operation. The clock generation section and the divider section l5 are known in the art. It consists of a clock generation circuit and a divider circuit to provide a clock signal to the board of the present invention.

The address decoder 17 is connected to the internal bus, and generates a selection signal so that the MPU 11 can control each element in the board. In the embodiment of the present invention, an address of the MPU 11 is generated. PAL (Programmable Array Logic) is implemented to provide selection signal according to signal and control signal.

The interrupt control unit 18 is connected to the internal bus to recognize an interrupt for processing a message transmission / reception process and to allow an interrupt response cycle of the MPU 11 to be performed.

DMAC 19 is a DMA controller connected to the internal bus and has four independent processing channels for sending and receiving messages. In the embodiment of the present invention, the MC68450 is used.

The DSUCC 20 is a multifunction serial communication controller connected to the internal bus and the DMAC 18 and having two independent channels for transmitting and receiving messages for sending and receiving messages. In the embodiment of the present invention, the SCN68562 is used. It was.

The signal loop control unit 21 is connected to the DSUCC 20 and the STG bus and the DLC connection control unit 25. The signal loop control unit 21 is a signal for the serial I / O (Seria Input / Output) and an external signal (STG) in the signal terminal. It is located at the point of connection between the bus and the DLC interface, and has the function of blocking the signal transmitted from the signal terminal board to the outside and looping back to the inside under the control of the status control register 24. Provides the function of self-test without affecting message input / output dedicated board, DLC interface, and other signal terminal boards.

The MFP 22 is connected to the internal bus and has a built-in asynchronous serial communication controller, three timers, input / output ports, and interrupt prioritization module of various causes, and in the embodiment of the present invention, MC68901. Was used.

The status recognition register 23 and the status control register 24 are connected to the internal bus, the MFP 22, and the DLC connection controller 25, respectively, to check the operation status of the board and to control various functions in the message transmission / reception process. In the embodiment of the present invention, the 16-bit register is configured to analyze the operation state of the signal terminal board and control the state to an appropriate state when necessary.

The DLC connection controller 25 is a functional block for exchanging signaling network messages with message transfer units of other switching stations by providing a connection function from the TDX-1 series electronic switchboard to the trunk module and has the following main functions.

First, a specific channel in the PCM of 2.04 Mbps is selected according to the setting value (0 to 31) of the selection switch in the signal terminal board.

Secondly, it operates dependently on the DLC interface connection, extracts the frame synchronization signal and the clock signal of the DLC interface, and generates control signals and frequency division clocks necessary for speed matching.

Third, it transmits and receives at 64Kbps to set data signal link according to international recommendation and has speed matching function to extract or insert message in specific channel of DLC interface.

The main functions of the functional blocks of the signal terminal board shown in FIG. 2 have been described so far. The linkage of each functional block and the overall operation procedure are as follows.

The signal terminal board blocks the data coming in from the DLC interface at the initial operation by the DCL connection controller 25 and controls the signal link state according to the interpretation of the level 3 message received on the STG bus. After receiving, it transmits a message (MSU) to the trunk line among the level 3 messages to be transmitted to the level 3 of the state side. The MPU 11 controls the reception channels of the DMAC 19 and the DUSCC 20 in operation, and the messages received from the level 3 on the STG bus are stored in a specific area of the SRAM 13 used as a buffer. The message to be interpreted by the signal link function (level 2) mounted on the signal terminal board and transmitted to the state level level 3 drives the DMAC 19 and the DUSCC 20 and is transmitted through the DLC connection controller 25. Since the message received from the DCL interface is the partner level 3 message, it is sent to the STG bus.

At this time, by using the control signal of the status control register, the transmitting end of the STG bus is opened and the transmitting end is closed at the end of the transmission to prevent the collision of signals only from the transmission of several signal terminal boards. In the transmission / reception process of the STG bus and DLC interface stages, the DMAC 19 and the DUSCC 20 inform each MPU 11 of the operation status as an interrupt signal, and the MPU 11 interrupts the interrupt control unit 18 via an interrupt control unit 18. Sends an interrupt response signal to the device that applied. The state recognition register 23 recognizes the operation state and performs the necessary control functions with the state control register 24, and the main operation state in the signal terminal board can be monitored using the serial asynchronous communication port of the MFP 22. .

Hereinafter, the detailed configuration and operation of the main functional block of the signal terminal board will be described in detail with reference to FIGS. 3 to 5.

FIG. 3 is a detailed circuit diagram of the interrupt controller of FIG. 2, where FIG. 3A is an interrupt recognition unit in the signal terminal board, and FIG. 3B is an interrupt response unit in the signal terminal board.

In the figure, 31 denotes a priority encoder, 32 denotes a decoder, 33 denotes a NAND gate, and 34 denotes an AND gate.

As shown in (a) of FIG. 3, an interrupt recognition unit is connected to a status control register, and if a DMAC interrupt, a DUSCC interrupt, and an MFP interrupt are required, a priority encoder for encoding the interrupt signal and outputting the corresponding interrupt signal to the MPU 11 is provided. LS148 was used in the embodiment of the present invention as the orderer. Therefore, when interrupts of various causes occur at the same time, a higher priority interrupt is applied to the MPU 11.

The interrupt response portion in the signal terminal board is a three-input NAND gate 33 connected to the MPU 11, a decoder 32 connected to the NAND gate and the MPU, and the decoder as shown in FIG. 3B. It consists of a three-input AND gate 34 connected to the output of the further. This circuit is hardware logic that recognizes an interrupt in the MPU 11 and gives a response signal to the device that generated the interrupt, and informs the corresponding device of the interrupt recognition of the MPU 11 in an interrupt response cycle. In the embodiment of the present invention, LS138 is used as the decoder 32.

4 is a detailed block diagram of the DLC access controller of FIG. 40a to 40d are input and output buffers, 41 is a channel counter, 42 is a control signal generator, 43 is a dip (DIP) switch, 44 is a channel comparator, 45 and 48 are serial / parallel converters, 46 and 50 is parallel / Serial converter 47 denotes a DUSCC and 49 denotes a latch.

)와 채널(Ch) 값을 발생시킨다.The channel counter 41 is connected to the DLC interface and is connected to the buffer 40a for inputting the synchronization signal FS and the buffer 40b for inputting the clock signal CLK.

) And channel (Ch) values.

A dip (DIP) switch 43 connects to the channel comparator 42 as equipped to allow hardware selection of a particular channel of the DLC interface channel.

The channel comparator 42 is connected to the channel counter 41 and the dip switch 43. When the set value of the switch 43 and the channel Ch value of the channel counter 41 coincide with each other, the channel select signal ( Ch-S).

,

)를 발생시킨다.The control signal generator 44 is connected to the channel counter 41 and the channel comparator 42, and the signals CLK1, CLK2, which are necessary for speed matching between 2.048 Mbps and 64 Kbps.

,

).

The first serial / parallel converter 45 is connected to the DLC interface and converts the parallel data into the buffer 40c for inputting 32 channel PCM data and the serial data connected to the control signal generator 44.

, 64K)에 따라 입력되는 병렬 데이타를 직렬 데이타로 변환하여 출력한다.A first parallel / serial converter 46 is connected to the control signal generator 44 and the first serial / parallel converter 45, and the control signal (

, 64K) is converted into serial data and output.

The DSUCC 47 is a multifunctional serial (serial) communication controller capable of performing independent transmission and reception.

The second serial / parallel converter 48 is connected to the DUSCC 47, and converts serial data inputted according to a 64 KHz clock signal into parallel data.

A latch 49 is connected to the second serial / parallel converter 48 and inputs and outputs the parallel data according to a synchronization signal FS for a 32 channel PCM.

)에 따라 입력되는 병렬 데이타를 직렬데이타로 변환하며, DLC인터페이스에 접속된 출력 버퍼(40d)를 통하여 PCM데이타를 송출한다. 이때 상기 송신데이타는 채널 선택신호(Ch-S)에 의해 32채널 PCM의 특정한 채널로 삽입된다.The second parallel / serial converter 50 is connected to the latch 49 and the control signal generator 44, and the control signals CLK2,

The parallel data inputted according to the above is converted into serial data, and the PCM data is sent out through the output buffer 40d connected to the DLC interface. At this time, the transmission data is inserted into a specific channel of the 32 channel PCM by the channel selection signal Ch-S.

5 shows the configuration of the signal loop control unit. In the embodiment of the present invention, LS157 is used. In case of self test of STG bus connection function and DLC interface connection function of signal terminal board, it performs connection function with message input / output dedicated board of Fig. 1, and finds the location of error in case of problems in connection operation with trunk module. It is useful to pay. On STG bus, signal terminal board operates dependently and uses receive clock.In case of self-test by loopback, signal signal and division signal clock signal can be used as independent test using signal terminal board's own operation clock. b) is used. The signal loop function is performed when necessary using the control signal a of the status control register. Even when the DLC interface is connected, it has the same signal loop function.

6 is a detailed configuration diagram of the bus error recognition and generation unit, where 61 is an OR gate, 62 is an AND gate, and 63 is a multivibrator.

The OR gate 61 outputs the OR of the reset signal c on the board and the signal d corresponding to two divisions of the MPU 11 operating frequency, and the AND gate 62 outputs the OR gate and the MPU. The address strobe (AS) signal e of (11) is ANDed and output. When the address strobe AS signal is not generated for a predetermined time by the multivibrator 63 connected to the output terminal of the AND gate 62, a signal is generated on the bus. The MPU 11 then recognizes the bus error signal, determines that it is a serious error of the control routine, and initializes the control routine in the signal terminal board.

Thus, the signal terminal board of the present invention as described above has a message for matching the STG bus connection function, the signal data link setting and control function, and the transmission speed difference between the STG bus and the signal data link for linkage with a level 3 module. Perform buffer management and monitor operation status of signal terminal board.

The present invention configured and operated as described above has the following effects.

It provides hardware connection technology that can transfer the function of message transmission unit of common line signaling system to TDX-1 series, which is a domestic electronic exchanger. In addition, the board of the present invention is designed to perform the signal data link (level 1) function and the signal link (level 2) function of the message transfer part, and the signal terminal board is configured to be multiplexed to the level 3 function control unit that is in charge of the signal network function. This improves the overall throughput of the message delivery unit.

Claims (7)

Interprets the message input through the STG bus at the message transfer part of the electronic switchboard, and performs the control function of the signal terminal status for the internal signal message between level 3 and level 2, and transmits the message to the status level 3 module. Is a signal terminal board that transmits through the STG bus using a specific channel of the trunk module DLC; The MPU 11 for accessing and controlling devices on the board through an internal bus, a programmable ROM 12 connected to the internal bus, a static RAM 13 connected to the internal bus, and the MPM 11. Bus error recognition and generation means (14), power supply and recovery, which are connected and monitor the operation status of the MPU to recognize the bus error caused by the operation error of the control software and inform the MPU 11 to restore the system to normal. Reset circuit means 16 for maintaining operation synchronization of each device in the board upon set request, clock generation and distribution means 15 for supplying a clock signal to each device on the board, and connected to the internal bus to the MPU ( An address decoding means 17 for generating a selection signal so that 11) can control each element in the board, and connected to the internal bus for interrupt processing of a message transmission / reception process; And an independent message transmission / reception message connected to the internal bus and the DMA control means 19, the DMA control means 19 connected to the internal bus, and allowing the interrupt response cycle to be performed. A serial communication control means (DSUCC) 20 having a function, connected between the serial communication control means 20 and the STG-bus, has a function of blocking an external signal transmitted from the board to the outside and looping back the inside. Signal loop control means 21, an MFP 22 connected to the internal bus, a state recognition register 23 connected to the internal bus and the MFP 22 to confirm an operating state in the board, the internal bus and the MFP 22 To the state control register 24 and the signal loop control means 21, the MFP 22, the state recognition register 23 and the state control register 24 to control the operation state in the board to an appropriate state. connect Level 1 and 2 functions of the common line signaling method message delivery unit comprising a DLC connection control means 25 for exchanging a signal network message with a message delivery unit of another switching station by providing a connection function to a trunk module. Signal terminal board for. 2. The interrupt control means (18) according to claim 1, wherein the interrupt control means (18) is connected to the internal bus and interrupt recognition means for priority encoding of the interrupt requests from the respective elements and outputs them to the MPU (11). Signal terminal board for implementing the level 1 and 2 functions of the common line signaling method message transmission unit, characterized in that it is connected to the interrupt response means for responding to the interrupt generating element the interrupt recognized by the MPU (11). 3. The interrupt recognition means according to claim 2, wherein the interrupt recognition means comprises a LS148 (31) which is a priority encoder, and the interrupt response means includes a NAND gate (33) connected to the MPU (11), the MPU (11) and a NAND gate. And a decoder LS138 (32) connected to (33), and an AND gate (34) connected to the LS138. The signal terminal board for implementing the level 1 and 2 functions of the common line signaling message transfer unit. The DLC connection control unit 25 is a channel counter 41 connected to the DLC interface through input buffers 40a and 40b, and a dip for hardware selection of a specific channel of the DLC interface channel. DIP) switch 43, the channel comparator 42 connected to the channel counter 41 and the dip switch 43, the control signal generator 44 connected to the channel counter 41 and the channel comparator 42, the control A first serial / parallel converter 45, the control signal generator 44 and the first serial / parallel converter connected to the DLC interface through a signal generator 44 and an input buffer 40c and inputting and converting PCM data; A first parallel / serial converter 46 connected to 45, a DUSCC 47 connected to the first parallel / serial converter 46, a second serial / parallel converter 48 connected to the DUSCC 47, the A latch 49 connected to a second serial / parallel converter 48, a latch 49 and a control signal generator 44 Signal terminal board for implementing the level 1 and 2 functions of the common-line signaling system message transmission unit, characterized in that consisting of a second parallel / serial converter (50) for converting and outputting data. 5. The method of claim 4, wherein the PCM data output from the second parallel / serial converter 50 is inserted into a specific channel of the 32-channel PCM by a channel select signal Ch-S. 6. Signal terminal board for negative level 1 and 2 functions. The signal terminal board according to claim 1, wherein the signal loop control means (21) comprises LS157. The OR gate 61 of claim 1, wherein the recognition and generation unit 14 of the bus performs an OR operation on the reset signal c in the board and the signal d corresponding to two divisions of the operating frequency of the MPU 11. ), An AND gate 62 for performing an AND operation on the output of the OR gate 61 and the address strobe signal e of the MPU 11, and a multivibrator 63 connected to an output terminal of the AND gate 62. Signal terminal board for implementing the level 1 and 2 functions of the common line signaling message transmission unit, characterized in that consisting of.

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