KR930002081Y1 - High speed parallel comparator - Google Patents

Abstract

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Description

High Speed Parallel Comparator

1 to 4 are examples for explaining the concept of the comparator.

5 is a block diagram of a conventional parallel comparator.

6 is a block diagram of a high speed parallel comparator according to the present invention.

* Explanation of symbols for main parts of the drawings

100, 201, 202, 302: Batter Oagate 203, 204: Inverter

205, 301, 401, 402: AND gate 302: Batano agate

403: Oagate

The present invention relates to a device design that finds MIN / MAX values in consideration of high speed, and more particularly, to a high speed parallel comparator that is not only fast but also provides regularity to easily handle bit expansion.

The prior art for the comparator uses a batanoa gate as shown in FIG. 1, and two batao gates 201 having respective inputs (10.0, 20.0) (10.1, 20.1) as in FIG. There is a configuration in which the output 70 of the AND gate 205 is connected to two input terminals of the AND gate 205 through the inverters 203 and 204 which are outputs of the 202.

In addition, as shown in FIG. 3, an additional output indicating a bit pattern indicating which is large or small, as well as an output of whether two numbers are not the same, is shown in FIG.

Referring to these operations, if the inputs 10 and 20 are 1 and 0, respectively, in FIG. 1, the output 70 of the batanoa gate 100 acts as a basic comparator indicating that two numbers are not equal. If the two inputs 10 and 20 are 1 and 1, respectively, the output 70 of the batteroa gate 100 is 0, indicating that the two numbers are the same.

In FIG. 2, when the inputs (10.0, 20.0, 10.1, and 20.1) are 10.0 = 0, 20.0 = 1, 10.1 = 1, and 20.1 = 0, respectively, it becomes 0 in the exclusive oragate 203 (204) and the endgate 205 The output 70 of is a two-bit extended basic articulator indicating that the two are not equal.

In Fig. 3, an additional output indicating which number is large or small is attached together with an output indicating simply whether the two yarns are the same.

That is, as shown in FIG. 3, the input 10.0 is connected to one input terminal of the AND gate 301 and the batteroa gate 302, and the input 20.0 is connected to the other input terminal of the batteroa gate 302. At the same time, the inverter 30 is connected to the other input terminal of the AND gate 301 and outputs 30 and 40 are generated at the AND gate 301 and the batteroa gate 302, respectively. Same as in

TABLE 1

In FIG. 4, the output 50 is generated at the oragate 403 which has a different input 30.1 from the output of the AND gate 401 having the two inputs 30.0 and 40.1, and the two inputs 40.0 and 40.1. The output gate 60 is generated in the AND gate 402 having the same, and the truth table is as shown in Table 2 below.

TABLE 2

Here, 50 to 60 represents "10", 10 total <20 total, "01" represents 10 total = 20 total, and "10" represents 10 total> 20 total.

However, there is the following problem in the bit extension as shown in FIG.

First, as the bit length increases, the operation speed may be slowed in proportion to the larger bit length. Second, there is a problem in that bit extension is not easy when applied to a large system.

The present invention solves the problem of the comparator configuration method according to the related art, and thus, the bit extension is very easy and the processing speed is also comparable to that of the conventional method of FIG.

In other words, when configuring an 8-bit comparator, the comparators 600 to 607 as shown in FIG. 3 and 8 and 7 comparators as shown in FIG. Is very fast.

Referring to Figure 6 describes the operation state as follows.

In the comparator 600 comparing 10.0 and 20.0, the result is an input of the comparator 610.

In addition, in the comparator 601 comparing 10.1 and 20.1, the result is expanded as an input of the comparator 610, and the case of 8 bits is illustrated.

If the 10 total bits (10.0 to 10.7) are set to "00000000" and the 20 total bits (20.0 to 20.7) are set to "00000000", the result of the final comparator 616 after each comparator is "01".

That is, when 10 total = 20 total, the outputs 50 and 60 are "01".

If the 10total bit is referred to as "00000011" and the 20total bit is referred to as "01000000", the result of the final comparator 616 after each comparator is "00".

Finally, when 10 total bits, that is, 10 total <20 total, the outputs 50 and 60 become "00".

When the "total bit" of 11111111 is "01010101", the result of the final comparator 616 after each comparator is "10".

That is, when 10 total> 20 total, the outputs 50 and 60 of the comparator 616 are "10".

Therefore, the high speed parallel comparator according to the present invention can find min / max within a fast operating time, and can greatly improve the operating speed when applied to a circuit requiring fast operating speed such as pattern matching. Has

Claims (1)

Comparators 600 to 607 that generate output by comparing inputs 10.0 to 10.7 and 20.0 to 20.7, respectively, and the comparators 600, 601, 602, 603, 604, 605, 606, 607. Comparators 610 to 613 generating output by comparing the respective outputs of the comparator, comparators 614 and 615 generating output by comparing the outputs of the comparators 610, 611, 612 and 613, and the comparator. And a comparator (616) for comparing the outputs of (614, 615) and generating outputs (50, 60).