KR930002066B1 - Clock generator for network synchronization - Google Patents

Abstract

The circuit processes the data transmitted between networks without loss by supplying clock locked to both the clock of an oscillator and the reference clock. It includes a processor interfacing circuit (1) for processing oscillation control signal and data from a processor, a control signal generator (2) for generating buffer enable signal and latch enable signal, a latch circuit (4), a OVCXO (7) for controlling the frequency of the output clock, and a buffer circuit (3) for buffering the oscillator control signal and data.

Description

Clock generator

1 is a circuit diagram of the present invention.

2 is a configuration diagram of a latch circuit.

3 is a configuration diagram of a manual operation circuit.

* Explanation of symbols for main parts of the drawings

1 processor interface circuit 2 control signal generation circuit

3: buffer circuit 4: latch circuit

5: visualization circuit 6: D / A conversion circuit

7: OVCXO 8: Output clock control circuit

9: manual operation circuit

The present invention relates to a clock generator for generating a clock synchronized with an external synchronization reference clock with a network synchronizer of an electronic exchange.

An object of the present invention is to compare a phase of a clock output from an oscillator in a phase locked loop with a synchronous reference clock equivalent to a reference frequency of a switched network extracted from externally input data, thereby allowing the processor to fix the phase of the oscillator clock to the synchronous reference clock. The oscillator control value is provided and the clock according to the oscillator control value is supplied to the inside of the electronic exchange so that the data can be processed without loss when transmitting data between networks in the switching network.

The present invention provides a processor interface circuit connected to a transmission line for transmitting and receiving oscillator control values and data (operation mode values, master code values, output clock enable signals), and a control signal transmission line to achieve the above object. Control signal generation circuit for generating control signals in the clock generator so as to receive the control signals RD, WR, decoder, and address and drive the enable terminals of the buffer circuit and the latch circuit. A latch circuit for latching the oscillator control value and data (operation mode value, master code value, output clock enable signal) output from the processor interface circuit by the signal, the oscillator control value and operation mode value and master code latched by the latch circuit. Visualization circuit that visualizes the value and analyzes the digital oscillator control value latched by the latch circuit Output to control the output clock by inputting the output of the OVCXO and OVCXO that generate the clock by the output value of the D / A conversion circuit and the D / A conversion circuit, and the output clock enable signal latched by the latch circuit, respectively. When the processor requests and stores the clock control circuit and the oscillator control values and data (operation mode values, master code values, and output clock enable signals) latched by the latch circuit, the processor interface is controlled by the control signals output from the control signal generation circuit. A buffer circuit for transmitting to the circuit and a manual operation circuit for generating a clock by manually controlling the OVCXO when the processor board is not operating are characterized in that the configuration.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a circuit diagram of the present invention.

In the figure, 1 is a processor interface circuit, 2 is a control signal generation circuit, 3 is a buffer circuit, 4 is a latch circuit, 5 is a visualization circuit, 6 is a D / A conversion circuit, and 7 is OVCXO (Ovenized Voltage Controlle-d X-tal Oscillator), 8 denotes an output clock control circuit, and 9 denotes a manual operation circuit.

By comparing the phase of the oscillator clock in the loop with the synchronous reference clock synchronized with the reference frequency of the switching network extracted from the external input data, the processor sets the oscillator control values and data (operation mode value, master When the code value and the output clock enable signal are provided to the clock generator, the processor interface circuit 1 of the clock generator receives it, and the control signal generator circuit 2 receives the control signals RD, WR, decoder, Address) to generate a control signal for driving the enable terminals of the buffer circuit 3 and the latch circuit 4, wherein the latch circuit 4 receives the oscillator control values and data received from the processor interface circuit 1; (Operation mode value, master code value, output clock enable signal) is latched by the latch enable signal outputted from the control signal generation circuit 2, The novelty control value is the visualization circuit 5 and the D / A conversion circuit 6, the operation mode value and the master code value are the visualization circuit 5, and the output clock enable signal is the output clock control circuit 8, respectively. send.

The visualization circuit 5 visualizes the oscillator control value and the master code value as 7 segment LEDs and the operation mode value as LEDs among the data received from the latch circuit 4, and the D / A conversion circuit 6 The output frequency of the OVCXO (7) is adjusted by converting the digital oscillator control value output from the latch circuit 4 to an analog value. The variation range of the analog value is + and -5V and the minimum control range is a digital value. About 0.15 mV.

OVCXO (Ovenized Voltage Controlled X-tal Oscillator) is a high crystal crystal oscillator that generates a basic clock of 32.768MHz. The frequency varies depending on the input voltage and the frequency characteristic has a negative transfer characteristic according to the applied voltage.

The output clock control circuit 8 is composed of AND logic gates and logically multiplies the oscillator clock output from the OVCXO 7 and the output clock enable signal received from the latch circuit 4 to output the OVCXO 7. In this case, the output clock enable signal remains at the logic level 'Low' state until the clock generated by the OVCXO 7 becomes constant (about 15 minutes after warming up and goes to the normal mode at power off-on). It is set so that it does not supply the clock to the system until the clock output from the oscillator is stable.

On the other hand, the buffer circuit 3 stores the data given by the latch circuit 4 to the D / A conversion circuit 6, the visualization circuit 5, and the output clock control circuit 8, when a request is received from the processor. It has a function of transmitting to the processor interface circuit 1 by the buffer enable signal output from the control signal generation circuit 2, the manual operation circuit 9 is a normal oscillator control value because the processor loses its function In case of failure, manually adjust the oscillator control value so that the system can supply normal clock.

2 is a configuration diagram of the latch circuit.

The latch circuit 4 includes a visualization circuit 5 and a D / A conversion circuit for applying a master code value, an operation mode value, an output clock enable signal, and an oscillator control value from the processor interface circuit 1 and visualizing the same. 6) The oscillator control value is transmitted by 8 bits and the input bit of the D / A conversion circuit 6 is 16 bits. Therefore, it is written to latch 1 and applied to the input terminal of latch 2 first. When input to the next latch 3, the input data of the latch 2 is also applied to the conversion circuit.

Latch 4 generates an operation mode value and a master code value, and latch 5 generates an output clock enable signal.

3 is a block diagram of a manual operation circuit.

When the switch is manually operated when a failure occurs in the processor, the output of the manual control circuit 13 transitions from a 'high' state to a 'low' state, and the preset signal generation circuit 15 is manually operated. The output circuit of the operation circuit 13 is monitored and a preset signal of a predetermined magnitude is generated when the output changes from a 'high' state to a 'low' state, and the counter circuit 16 is freed by the preset signal. Is set. The rising switch 11 and the falling switch 12 are devices for increasing or decreasing the oscillator control value output from the preset counter circuit 16 as described above. The timer 14 is provided by signaling a state change to a state, and the timer 14 changes the irregular state change signal generated by the rising switch 11 and the falling switch 12 into a pulse having a constant time size. The counter circuit 16 can increase or decrease the oscillator control value by inputting to the up and down input terminals of 16).

The monitor circuit 18 enables and disables the latch clock generation circuit according to whether the manual operation circuit 13 is driven, and the latch clock generation circuit 17 outputs the output of the monitor circuit 18 to 'Low'. In the case of a state, the output of the timer 14 is monitored to generate a latch clock whenever a pulse occurs, and the latch circuit 19 is a clock generated by the latch clock generation circuit 17 of the counter circuit 16. By latching the oscillator control value and performing the same function as the latch circuit 4 of FIG. 1, when the processor loses its function and cannot supply the normal oscillator control value, the oscillator control value is manually adjusted to adjust the normal clock to the system. Make it available.

The present invention is configured as described above so that the processor generates the clock according to the oscillator control value to provide the phase of the oscillator clock is fixed to the synchronous reference clock to supply to the system so that data can be processed without loss during the transmission of manganese data, The oscillator control value and master code value are visualized by the 7-segment LED, respectively, and the operating mode value is visualized by the LEDs.When the clock generated by the oscillator is in a constant state (about 15 minutes after warming up and goes to normal mode when power off-on) It is designed to provide a stable clock to the system by preventing the output from being outputted and manually supplying the clock even when the processor loses its proper function.

Claims (4)

Processor interface circuit 1 for receiving oscillator control values and data (operation mode values, master code values, output clock enable signals) from the processor, and receiving control signals (RD, WR, decoder, address) from the processor A control signal generation circuit (2) for generating an enable signal and a latch enable signal, and oscillator control values and data (operation mode values, master code values, output clock enable signals) received from the processor interface circuit (1); A latch circuit 4 latching by the latch enable signal output from the control signal generation circuit 2, and a D / A conversion circuit 6 for analog-converting the digital oscillator control value received from the latch circuit 4; ), The OVCXO 7 for adjusting the frequency of the output clock by the analog oscillator control value received by the D / A conversion circuit 6, and the oscillator control value and data received by the latch circuit 4 (operation). A buffer that stores a mode value, a master code value, and an output clock enable signal, and transmits the buffer enable signal output from the control signal generation circuit 2 to the processor interface circuit 1 when a request is received from the processor. A clock generator comprising: a circuit (3). The clock generation method according to claim 1, further comprising a visualization circuit (5) connected to the latch circuit (4) to visualize an oscillator control value and a master code value with a seven segment LED and an operating mode value with an LED. Device. 2. The OVCXO (7) according to claim 1, wherein the output clock enable signal connected to the latch circuit (4) and the OVCXO (7) and the output of the latch circuit (4) and the output of the OVCXO (7) are logically multiplied. And an output clock control circuit (8) for controlling a clock to be output by the clock generator. 2. A manual circuit according to claim 1, which is connected to the latch circuit (4) to manually adjust the oscillator control value so that the processor can supply the normal clock to the system in case the processor loses its function and cannot supply the normal clock to the system. And a control circuit (9).

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