KR930001905B1 - Manufacturing method of photo diode for improved photo-fiber communication - Google Patents
Manufacturing method of photo diode for improved photo-fiber communication Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000835 fiber Substances 0.000 title 1
- 239000004642 Polyimide Substances 0.000 claims abstract description 43
- 229920001721 polyimide Polymers 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 41
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 238000004380 ashing Methods 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims abstract description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 20
- 238000001459 lithography Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 9
- 229910004205 SiNX Inorganic materials 0.000 claims description 8
- 230000003667 anti-reflective effect Effects 0.000 claims description 7
- 230000003287 optical effect Effects 0.000 claims description 4
- 230000006641 stabilisation Effects 0.000 claims description 3
- 238000011105 stabilization Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000002161 passivation Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009713 electroplating Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009429 electrical wiring Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 244000025254 Cannabis sativa Species 0.000 description 1
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- 235000005607 chanvre indien Nutrition 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000011487 hemp Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
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Abstract
Description
제1a도는 본 발명에 의한 포토 다이오드의 단면 구조도.1A is a cross-sectional structure diagram of a photodiode according to the present invention.
제1b도는 무반사막이 없는 포토 다이오드의 단면 구조도.1B is a cross-sectional structure diagram of a photodiode without an antireflection film.
제2도는 본 발명에 의한 포토 다이오드의 제조 공정을 나타낸 단면도.2 is a cross-sectional view showing a manufacturing process of a photodiode according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : n-InP 기판 2 : i-GaInAs1: n-InP substrate 2: i-GaInAs
3 : p-GaInAs 4 : 폴리이미드(Polyimide)3: p-GaInAs 4: polyimide
5 : SiO2산화막 6 : p-면 전극패드5: SiO 2 oxide film 6: p-plane electrode pad
7 : n-면 전극패드 8 : 와이어7: n-side electrode pad 8: wire
9 : SiNx 무반사막9: SiNx antireflection film
본 발명은 광통신 시스템에 사용되는 수광소자의 제조방법에 관한 것으로, 특히 GaInAs/InP핀 포토 다이오드(PIN photo diode) 및 애벌런시 포토 다이오드(avalanche photodiode : APD)등 수광소자의 암전류(dark current)를 저감시키고 평면화된 포토 다이오드 제조방법에 관한 것이다.BACKGROUND OF THE
종래의 경우는 메사(mesa)를 형성하고 p-면 전극을 형성한 후, 폴리 이미드(Polyimide)로 보호막을 입혀 표면에 노출되는 pn접합부를 보호하여 표면 누설전류를 제거하였는데, 상기 과정에서 pn접합부에 전극 패드가 형성되어 있음으로 해서 와이어 본딩(wire bonding)시에 가해지는 충격으로 인해 pn접합부에 결정 결함이 유도되어 암전류(dark current)가 증가 하였으며 이를 피하기 위해 전기도금등의 방법으로 2㎛이상의 두꺼운 금속층을 형성하여 충격을 완화하는 방법으로 사용하여 누설전류를 감소시켰다. 그러나 이 방법으로 포토 다이오드를 제작할 경우, 폴리이미드(polyimide)는 pn접합부를 둘러싸서 단지 표면 누설전류를 제거해 주는 역할 밖에 하지 못하며, 와이어 본딩(wire bonding)시에 가해지는 충격을 완화하기 위해서는 또다른 금속 층을 형성하기 위한 전기도금을 필요로 함에 따라 리쏘그라피(lithography)를 여러번 해야하는 공정의 복잡성 문제를 내재하고 있었다. 또한 표면 보호막으로만 사용된 폴리이미드(polyimide) 코딩공정시에도 폴리이미드를 코팅한 후 활성층(Active area)영역에는 폴리이미드를 제거해야 하는데, 이 공정시에 포토 레지스터를 입히고 복잡한 열처리를 한후 마스크 작업을 거쳐 에칭하는 방법을 사용하였으나, 이 방법 또한 폴리이미드를 화학용액에서 에칭하기 위해서는 낮은 온도에서 열처리를 해야하며, 또 이미다이즈(immidize)시키기 위해서 패턴을 형성한후 높은 온도에서 다시 열처리를 해야하는 공정의 복잡성 문제를 내재하고 있다.In the conventional case, after forming a mesa and forming a p-plane electrode, a protective film was coated with polyimide to protect the pn junction exposed on the surface, thereby removing surface leakage current. Due to the electrode pads formed at the junctions, the impacts applied during wire bonding induced crystal defects at the pn junctions, resulting in an increase in the dark current. The above-mentioned thick metal layer was formed and used as a method of alleviating the impact to reduce the leakage current. However, when the photodiode is fabricated in this way, the polyimide only serves to remove the surface leakage current by surrounding the pn junction, and another method to mitigate the impact applied during wire bonding. The need for electroplating to form metal layers inherent in the complexity of processes requiring multiple lithography. In addition, during the polyimide coding process used only as a surface protective film, polyimide should be coated and then the polyimide should be removed from the active area. In this process, a photoresist is applied and a complex heat treatment is performed for masking. Although the etching method is used, this method also needs to be heat-treated at low temperature in order to etch the polyimide in a chemical solution, and to heat-treat at a high temperature after forming a pattern to imidize the polyimide. The complexity of the process is inherent.
따라서 본 발명은 상기의 문제점을 제거하기 위해 안출한 것으로서, 간단한 공정으로 폴리이미드층을 형성하여 표면에 노출된 pn접합부를 보호하고 상기 폴리이미드층 상에 전극을 형성시킴으로써 pn접합부에 전극 형성시 요하는 전기도금을 하지 않고서도 와이어 본딩시 증가되는 누설전류를 제거하여 소자의 암전류(dark current)를 저감시키는 포토 다이오드 제조방법을 제공함에 본 발명의 목적을 두고 있다.Therefore, the present invention has been made in order to eliminate the above problems, by forming a polyimide layer in a simple process to protect the pn junction exposed on the surface and to form an electrode on the polyimide layer to form the electrode on the pn junction It is an object of the present invention to provide a method for manufacturing a photodiode that reduces the dark current of a device by removing leakage current increased during wire bonding without electroplating.
본 발명은 상기 목적을 달성하기 위하여, 본 발명에 따른 광통신용 포토 다이오드 제조방법은 n-형 GaInAs기판(1)상에 i-GaInAs층(2) 및 p-GaInAs층(3)을 성장시켜 pn접합을 형성하도록 하는 pn접합 형성공정과, 리쏘그라피(lithography)를 1회 실시한 후 메사 에칭(mesa etching)을 수행하는 메사에칭 공정과, 표면에 노출된 pn접합부의 표면안정화(passivaition)를 위해 전면에 폴리이미드(4)를 코팅하는 폴리이미드 코팅 공정과, 상기 폴리이미층(4)상에 SiO2산화막(5)을 증착하는 산화막 코팅공정과, 리쏘그라피(lithography)를 1회 실시하고 상기 SiO2산화막(5)을 에칭하여 패턴화 한후, 폴리이미드(4)를 플라즈마 애싱(plasma ashing) 방법으로 SiO2패턴과 같은 패턴으로 형성하는 공정과, 폴리이미드층(4) 상의 SiO2산화막(5)을 제거하지 않은채 그 상부의 전면에 실리콘 나이트 라이드(SiNx)를 도포하는 무반사막(9) 형성공정 및, pn접합부의 전극이 닿을 부분만 리쏘그라피(lithography)를 통해 무반사막(9)를 제거하고 리쏘그라피를 1회 더 실시하여 p-면 금속을 증착한 다음 리프트 오프방법으로, 폴리이미드층(4) 상부에 위치한 상기 무반사막(9) 상에 직접 전극 패드(6)를 형성하는 전극 패드 형성공정을 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for manufacturing an optical communication photodiode according to the present invention by growing an i-GaInAs layer (2) and a p-GaInAs layer (3) on an n-type GaInAs substrate (1). Pn junction formation process to form a junction, mesa etching process to carry out mesa etching after performing lithography once, and front surface stabilization (passivaition) of the pn junction exposed on the surface A polyimide coating process for coating the polyimide (4) on the substrate, an oxide film coating process for depositing the SiO 2 oxide film (5) on the polyimide layer (4), and lithography once to perform the lithography. After etching and patterning the 2
이하 첨부한 도면을 참조하여 본 발명의 실시예를 상세한 설명한다. 제1a도는 본 발명에 의한 포토 다이오드의 단면구조를 나타낸 것으로서, 도면에서 1은 n-InP기판, 2는 i-GaInAs층, 3은 p-GaInAs층, 4는 폴리이미드(polyimide)는 5는 SiO2는 산화막, 6은 p-면 전극 패드, 7은 n-면 전극, 8은 와이어, 9는 SiNx무반사막을 각각 나타내며, 제1b도는 무반사막(9)이 없는 포토 다이오드의 단면 구조를 나타낸 것이다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1a shows a cross-sectional structure of a photodiode according to the present invention, in which 1 is an n-InP substrate, 2 is an i-GaInAs layer, 3 is a p-GaInAs layer, 4 is a polyimide, 5 is SiO 2 is an oxide film, 6 is a p-plane electrode pad, 7 is an n-plane electrode, 8 is a wire, 9 is a SiNx antireflection film, and FIG. 1b shows a cross-sectional structure of the photodiode without the
제2도는 본 발명에 의한 포토 다이오드의 제조 공정을 나타낸 것으로서, 도면의 부호는 제1a도의 경우와 동일하게 사용하였으며, 본도의 제2a도 내지 제2d도를 이용하여 제조공정을 순서대로 설명하면 다음과 같다.2 is a view illustrating a manufacturing process of a photodiode according to the present invention, and reference numerals of the drawings are used in the same manner as in FIG. 1A, and the manufacturing processes are sequentially described using FIGS. 2A to 2D of the present drawings. As follows.
우선 n-형 InP기판(1)위에 i-GaInAs(2)를 격자정합이 이루어지도록 LPE(Liquid Phase Epitaxy) 또는 MOCVD(Metal Organic Chemical Vapor Deposition) 방법으로 성장한 후 Zn확산으로 p-형 GaInAs(3)를 형성하거나, n-InP기판(1)위에 i-GaInAs(2) 및 p-GaInAs(3)를 차례로 성장하여 pn접합이 이루어지도록 한다(제2a도).First, i-GaInAs (2) is grown on the n-type InP substrate (1) by LPE (Liquid Phase Epitaxy) or MOCVD (Metal Organic Chemical Vapor Deposition) method, followed by pn-type GaInAs (3) by Zn diffusion. ) Or i-GaInAs (2) and p-GaInAs (3) are sequentially grown on the n-InP substrate (1) to form a pn junction (FIG. 2a).
상기 공정후 pn접합의 정전용량(junction capacitance)이 작아지도록 리쏘그라피(lithography)작업을 하여 메사에칭(mesa etching)을 한다(제2b도).After the process, lithography is performed so that the junction capacitance of the pn junction is reduced by mesa etching (FIG. 2b).
상기 메사에칭 공정후 표면에 노출되는 접합부의 표면 안전화(passivation)를 위해 전면에 폴리이미드(polyimide)(4)를 코팅하고(제2c도), 상기 폴리이미드의 에칭공정을 간단하게 하기위해 화학증착방(chemide vapour deposition chamber)내에 시료를 넣고 온도를 올려주어 폴리이미드(polyimide)의 이미다이즈(immideze)와, 상기 폴리이미드의 상부에 SiO2막(5)의 증착을 차례로 수행한다(제2d도, 제2d'도, 제2d"도).After the mesa etching process, a polyimide (4) is coated on the front surface for passivation of the joint exposed to the surface (Fig. 2c), and chemical vapor deposition is used to simplify the etching process of the polyimide. The sample was placed in a chemical vapor deposition chamber and the temperature was raised to sequentially imideide polyimide and deposit a SiO 2 film 5 on top of the polyimide (2d). Degrees, 2d 'degrees, and 2d "degrees).
상기 SiO2(5)증착 공정후 리쏘그라피(lithography)를 1회 실시하여 SiO2산화막(5)를 BOE(Buffered Oxide Etchant) 용액에서 에칭을 하여 패턴(Pattern)화 한후, 플라즈마 애싱 장비(plasma ashing machine) 내에서 폴리이미드를 상기 SiO2패턴과 같이 패턴화 함으로써 마스크 오프닝(mask opening) 공정과 플라즈마 애싱(plasima ashing) 공정을 수행한다.After the SiO 2 (5) deposition process, the lithography was performed once to form a pattern by etching the SiO 2 oxide film 5 in a BOE (Buffered Oxide Etchant) solution, followed by plasma ashing equipment (plasma ashing). The masking process and the plasma ashing process are performed by patterning the polyimide in the machine as in the SiO 2 pattern.
이때 SiO2를 패턴화 하기 위해 리쏘그라피용으로 도포한 포토래지스트(photo resist)는 폴리이미드의 패턴화 과정에서 플라즈마(plasma)에 의해 같이 제거되므로 별도의 포토 레지스트 제거 공정이 필요없다.At this time, the photoresist coated for lithography to pattern SiO 2 is removed by plasma during the patterning of the polyimide, so a separate photoresist removal process is not required.
폴리이미드(polyimide)층 (4)상의 SiO2산화막(5)를 제거하지 않은채, 그 상부의 전면에 걸쳐서 실리콘 나이트라이드(SiNx) 무반사막(9)을 PECVD(Plasma Enhanced Chemical Vapor Deposition)등의 방법으로 코팅하여 형성한다.(제2e도).Without removing the SiO 2 oxide film 5 on the
상기 SiNx무반사막(9) 형성공정후 리쏘그라피(lithography)를 1회 실시하여 pn접합을 형성하는 p-GaInAs(3)윗면의 전극이 닿을 부분만 SiNx무반사막을 제거하고, 리쏘그라피를 1회 더 실시하여 p-면금속을 증착한 다음 리프트-오프(lift-off) 공정으로 전극을 형성하게 되는데 이때 폴리이미드층(4) 상부에 위치한 무반사막(9) 상에 전극 패드(6)가 형성되도록 함으로써 성능이 향상된 포토 다이오드를 제작한다.After the process of forming the
다른 방법과 비교하여 본 발명이 갖는 특징을 들면 다음과 같다. 첫째, 실리콘 나이트라이드(SiNx)의 두께를 조절하여 무반사막을(9)을 형성한다.The features of the present invention compared with other methods are as follows. First, the
둘째, 종래의 경우 p-GaInAs(3) 상에 형성되던 전극 패드(6)를 폴리이미드(4), SiO2산화막(5), SiNx무반사막(9)의 순으로 형성되는 부도체(insulator) 상에 형성된다.Second, in the conventional case, the electrode pad 6 formed on the p-
셋째, p-GaInAs층상의 전극에서 부도체(insulator)상의 전극 패드(6)로 전기적 배선을 연결할때 제1b도의 목부분(10)보다 제1a도의 목부분(11)곡률이 휠씬 완만하게 형성됨에 따라 금속전기 배선이 용이하다.Third, when the electrical wiring is connected from the electrode on the p-GaInAs layer to the electrode pad 6 on the insulator, the curvature of the neck portion 11 of FIG. 1a is smoother than that of the
상술한 바와같은 본 발명의 효과를 열거하면 다음과 같다.Enumerating the effects of the present invention as described above is as follows.
가. 포토 다이오드 제조공정에서 pn접합부의 표면 안정화(passivation) 용도를 폴리이미드를 사용하는 경우 수광 부분 및 전극 접촉부분의 폴리이미드 제거 공정시 산화막(SiO2등)을 에칭 마스크로 하여 플라즈마 애싱(plasma ashing)의 방법으로 폴리이미드를 제거함으로써 복잡한 열처리 과정을 간단화 한다.end. In case of using polyimide for surface passivation of pn junction part in photodiode manufacturing process, plasma ashing is performed by using an oxide film (SiO 2 etc.) as an etching mask during polyimide removal process of light receiving part and electrode contact part. The complex heat treatment process is simplified by removing the polyimide by the method.
나. 폴리이미드 및 SiO2산화막 상부에 형성된 SiNx무반사막 상에 본딩 패드(bonding pad)를 형성함으로써 와이어 본딩시 가해지는 충격을 pn접합부가 아닌 곳으로 유도하여 전기도금 공정을 배제하도록 한다.I. By forming a bonding pad on the SiNx anti-reflective film formed on the polyimide and SiO 2 oxide film, the impact applied during wire bonding is induced to a place other than the pn junction to exclude the electroplating process.
다. 폴리이미드 위에 SiO2코팅하고 그 상부 즉 pn접합부 밖에 전극 패드를 형성할때, 폴리이미드 및 SiO2막의 두께를 합친 총 두께가 두꺼울수록 전기적 배선이 어렵게 되나, SiNx무반사막을 증착하여 전기적 배선부위를 완만하게 하여 수율을 증대시킨다.All. When SiO 2 is coated on the polyimide and the electrode pad is formed on the upper part, i.e., outside the pn junction, the thicker the total thickness of the polyimide and SiO 2 film becomes, the more difficult the electrical wiring is. To increase the yield.
라. 와이어 본딩을 pn접합부 밖에 형성하도록 하여 소자의 면적을 작게하고 정전용량을 감소시켜 고속동작을 수행하는 포토다이오드를 제공한다.la. The wire bonding is formed outside the pn junction to provide a photodiode that performs a high speed operation by reducing the area of the device and reducing the capacitance.
마. 평면형 수광소자를 요하는 패키징 및 광수신 모듈에 대해 값싸고 쉽게 제작할 수 있는 평면화된 메사형 포토 다이오드(mesa type photochiode)를 제공한다.hemp. The present invention provides a planarized mesa type photochiode that can be manufactured inexpensively and easily for packaging and photoreceiving modules requiring a planar light receiving device.
바. 전기도금에 배제, 폴리이미드 코팅 공정의 단순화로 칩 제조단가를 낮추고, 와이어 부착공정이 용이하여 패키징 간격을 절감한다.bar. Eliminating electroplating, simplifying the polyimide coating process lowers the chip manufacturing cost, and facilitates the wire attachment process, thus reducing the packaging interval.
또한 본 발명을 광수신 OEIC(Optoelectronic Integrated Circuit) 포토 다이오드와 트랜지스터를 금속 배선으로 연결할때, 누설전류 저감, 표면안정화(passivation) 및 금속배선과 반도체 분리용으로 폴리이미드를 사용할 경우 핀 포토 다이오드와 트랜지스터 사이의 높이차에 따른 어려움을 극복하도록 한다.In addition, when the present invention connects a photoreceiving optoelectronic integrated circuit (OEIC) photodiode and a transistor with metal wiring, a pin photodiode and a transistor when polyimide is used for leakage current reduction, surface stabilization, and metal wiring and semiconductor separation. To overcome the difficulties caused by the height difference between.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019900005908A KR930001905B1 (en) | 1990-04-26 | 1990-04-26 | Manufacturing method of photo diode for improved photo-fiber communication |
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