KR920022800A - High Gradation Halftone Processing System Using Image Processor - Google Patents

Abstract

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Description

High Gradation Halftone Processing System Using Image Processor

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2 is a block diagram of a high gradation halftone image processing system according to the present invention;

3 is a detailed configuration diagram of FIG.

4 is an exemplary diagram of a 64 gradation pattern matrix according to the present invention;

5 is a control flowchart according to the present invention.

Claims (3)

In a high gradation halftone image processing system using an image processor, a high gradation halftone processing control signal is output, and a line sync and page sync signals are output according to the input of a single line processing completion signal to generate high gradation halftone image data. Is connected between the CPU 145 and the CCD 150, and the CPU 145 for controlling the control, the CCD 150 for scanning the document with the scan control signal, and converting the document's harmonic into an electrical signal. The CCD 150 is driven in response to the halftone processing control signal and the driving control signal, and receives the analog signal inputted to correct the shading waveform and smoothes the shading waveform at the same time. DIPP 155 for outputting image signal IOUT, absolute lump potential value VBL, clock T / RCLK, and absolute lump potential value VBL and waveform corrected shading output from DIPP 155 signal A high gradation medium that encodes the smoothed analog image signal 1OUT with high gradation digital image data on the basis of (DAO) and outputs it as binarized high gradation halftone image data under the control of the CPU 145. High gradation half-tone processing system using an image processor, characterized in that consisting of the image processing unit 160. The analog image signal (1OUT) according to claim 1, wherein the high gray scale intermediate processing section (16) outputs the waveform corrected shading signal (DAO) output from the DIPP (155), and the absolute black level value (VBL). ) And encodes and outputs only the smoothed analog image signal 1OUT of the shading signal DAO and the absolute black level value VBL by digital clock data by the input clock T / RCLK. A pattern address for generating an halftone pattern address by inputting an ADC 180, a clock (T / RCLK) output from the DIPP 155, a line sink output from the CPU 145, and a page sink. Generator 200, a memory 220 for storing halftone data in a predetermined address area, and outputting halftone pattern data according to an address generated and input from the pattern address generator 200, and the ADC Image data and memory output from 180 High gradation halftone image processing system using an image processor, characterized in that the comparator 240 for outputting the binarized high gradation halftone image data by comparing the level of the halftone data output from the). The method of claim 2, wherein the pattern address generator 200 is cleared by the input of the line sink and counts the input of the clock T / RCLK to generate an open dress CA for accessing one line of pattern data. The first counter 202 and the second counter 204, which generate until the page sink is input, comprise a row address RA that counts the line sync and designates the next line. High gradation halftone image processing system. ※ Note: The disclosure is based on the initial application.