JPS5890863A - Image converter - Google Patents

Abstract

PURPOSE:To perform variable magnification processing of a picture signal with a simple constitution, by changing the number of picture elemnts of a picture element data. CONSTITUTION:A signal corresponding to one scanning line of a picture digital signal is stored in a memory M1 under the control of a memory controller MC1 via a data bus DB. Information relating to the ratio to be variably magnified is set to a clock controller CCL to control frequencies of clock signals generated from clock generators CG1 and CG2 according to the ratio of variable magnification. A digital signal from the memory M1 is applied to a D/A converter CDA in synchronizing with the clock signal from the clock generator CG1 and also to an integrator IL. The integrator IL performs integration in synchronizing with the clock signal from the CG2 and the output is stored in a memory M2 via an A/D converter CAD. The A/D converter CAD is operated in synchronizing with the clock signal from the CG2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method and apparatus for scaling and converting an image signal and outputting the same.

In recent years, CCD of the original images of Dokiemento has been released.
It has been announced that the temple's image sensor will convert the signal into an electrical signal and digitize it into i0.
It has been announced that this digitized image signal will be stored in memory and transmitted.

By the way, for example, when printing or displaying a collection of 12 images, the size of the place where the 2111i image should be inserted in the first image should match the size of the second image to be inserted in that part. There is.

If the size of the place to be inserted and the size of the image to be inserted are different, it is necessary to change the size of one to make them match.

Then, it is necessary to transfer the scaled digital signal of the second image to a memory area where the digital signal of the first image is stored and synthesize it. To reproduce this synthesized good image, the synthesized digital signal stored in the memory area is transferred to an output device such as a laser printer and fluorinated.

As mentioned above, when combining images of different sizes, it is necessary to change the size of the images without converting the pixel density.

Furthermore, in the case of connecting different devices such as a facsimile type device and a laser printer for computer output, the pixel density must be converted.

Typical facsimile pixel density is 8 pixels/- or 1
On the other hand, in laser printers for outputting conoviators, approximately 9.45 ui/2 (240 pixels/inch) is widely used. So, for example, 8
- Image signal transmitted by plain/■ facsimile 9.4
When output and displayed on a 5 pixel/■ laser printer, the image will be 8/9.45 (-0,85) times smaller.
In order to round the image and output it with a normal display, it is necessary to convert the pixel density.In such a case, a possible way to convert the pixel density is to use a combiator to process it in software. However, this method has the disadvantage that it takes time to scale the image and convert the pixel density because it has to be calculated and processed pixel by pixel. However, it takes a long time, ranging from tens of seconds to several minutes.

Also, in order to make it possible to change the magnification almost continuously, rather than by a number II#i such as 2x, 1/2, etc., the software program and peripheral node configuration would be extremely complicated. It is extremely difficult to perform transformation processing on the acquired image data, and I am not aware of any reports on this.The object of the present invention is to eliminate the above-mentioned drawbacks and provide a nine-image processing method or apparatus. The present invention is directed to a method or device for processing a 4 mm GE signal with a simple configuration, and a device for processing image data having halftones. The present invention is an improvement of an image conversion method or device that can change the magnification without changing the synchronization signal of an output device such as a printer. In addition to improvements, the present invention resides in an improvement of an image conversion method or device capable of continuously variable magnification, and the present invention also provides a tmag@process method for processing edges of digital pixels with high precision and reliability during variable magnification processing. This article also applies to an img process method or apparatus that processes digital Jmag@ signals using a node configuration.

In addition, the present invention is an imgg/processor that can reproduce images of the same size even with input/output devices having different pixel densities.
A 1 kll digital signal transferred serially in the scanning direction is converted into an n2 digital signal having a speed different from that of the original serial first digital signal, as an analog signal representing each pixel once. In this case, the analog signal representing the density of each pixel is averaged by integrating it in synchronization with the speed of the receiving side. Note that when each pixel in the image digital signal only represents whether it is white or black, the +01 path configuration before and after the circuit that performs integration becomes simple.

The present invention will be described in detail below using the drawings.

FIG. 1 shows a block diagram of one embodiment of the present invention. In the figure, a data bus DB and an address bus An are commonly used as pass lines of a combiator COM that processes image signals. The image digital signal is a signal corresponding to one scanning line (for example, a scan line in one scan of document reading 9 by COD) and is sent to the first memory under the control of the controller 9ycl via the data bus DB. The clock controller CCL is set with information regarding the scaling ratio, and the first clock generator CGI and the first clock generator CGI are 2 Controls the frequency of the clock signal generated from the clock generator CG2 ◇ Edge signal C3lIK from the first clock generator CGI Synchronously, the good image information stored in the first memory M1 is
Digital signal SDI via memory controller [1
The signal is supplied to a digital-to-analog converter (hereinafter referred to as D/A converter CL) A as a parallel 2-bit code (for example, 2 bits in parallel per 1# image). 1st lock generator CG
In synchronization with the clock signal C812 (Fig. 4) from I,
The D/A converter cDk is the digital signal SD of my information.
Convert I to an analog signal and output the analog output signal S.
A is supplied to the integrator IL. In addition, digital signal 51) 1
In the case of 200 million black and white signals, there is no need for a D/A converter, and it is sufficient to connect it to the integrator IL via a simple current amplifier. The integrator IL performs integration in synchronization with the clock signal C821 (Figure 44) from the second clock generator CG2, and supplies the integrated output signal 8I to an analog-to-digital converter (hereinafter referred to as a conmeter). The output signal SI is converted into a digital signal SD2 in synchronization with the clock signal C822 from the second clock generator CG2. Furthermore, the output signal SI is converted into a digital signal SD2 in synchronization with the clock signal C823.
It is stored in the second memory M2 under the control of the memory controller yc2. As a result, the number of pixels in one line of the memory M1 becomes the same as the first memory M1. The frequency is increased or decreased according to the ratio of the frequency of the second clock generator and stored in M2.
The clock generator CGI is the same, but the pulse generation time is shifted to account for delays in circuit production. Similarly, the clock signals C821, C822 and C823 from the second clock generator CG2 have the same frequency but one phase is slightly different from each other. ! FIG. 2 is a detailed block diagram showing a specific example of L. FIG. In the figure, the input amplifier circuit Al is an amplifier circuit formed by a combination of a well-known operational amplifier Ii & OPI and resistors R1 and R2. The integrating circuit ILC has a circuit pair consisting of a resistor R3 and a capacitor C1, and similarly has a resistor i! R4 and capacitor C2 form a pair, and the circuit is connected in parallel to variable gain amplifier A2 via resistors R5 and R16. Semiconductor switches 81 and 82 are connected in parallel to both ends of the capacitors C1 and CG2, respectively, and are controlled on and off by the output signal of the 7 lip-flop FF. The variable gain amplifier AVG is connected to the operational amplifier OP2 and the resistor. R7 and R8 constitute a voltage 7 lower.

A semiconductor variable resistance semiconductor element vR is connected between the common connection point CP of both resistors R7 and R8 and the ground. Then, the second clock is generated -! The clock signal C821 from CG2 is supplied to the clock input terminal of the 7 lip-flop FF, and is also supplied to the frequency-voltage converter (hereinafter referred to as controller) CF'V. ◇Output of the counter converter CFV teeth.

The operation of the integrator IL having the above configuration will be explained with reference to FIG. As mentioned above, the image data signal 8 is generated by the clock C812.
It is assumed that the frequency of the clock of the second clock generator CGI, which is outputted from A and inputted to iL, is twice that of the second clock generator CG, and that twice the magnification is reproduced and output. I'll do the fourth one again. In the master digital data 8131, each (t,
o) corresponds to t(01o)* (is t).

Since the state of the seven lip-flops FF is inverted every clock of the clock signal C821, both switches 81 and 82 are turned on and off alternately. Therefore, the analog signal SA amplified by the input amplifier circuit A1 is integrated by the capacitor C1 or C2 on the side of both switches 81 and 82 that are turned off, and the next clock sickle is 0.
0 integrated by the other capacitor. Therefore, the integrator circuit I
In LC, serial No. 1- without any downtime,
0 integrated every period of the cylinder, so from ILC,
The output is similar to the SI shown in FIG. 4 and has twice the number of pixels. This output is amplified and level-corrected by amplifier A and becomes tSI with the original halftone maintained. This 8I is converted to digital code SD* (e.g. Hebit's TOs s TO- by converter CAD). Then, the doubled round pixel data Sj) is stored in the 1-line memory M2.
The output voltage is changed according to the clock frequency of the variable resistor VR, so the gain of the variable gain amplifier is determined by the clock signal C821.
It is controlled by the frequency of As a result, the ILC output is 1. be
It is possible to correct the difference in the level ratio of c from the original data. With the gain controlled in this way, the voltage output integrated by the integrating circuit ILC is amplified'
t&, A/Supplied to the Coiverter CAD. At this time, the integrated output signal 8I, which is an analog signal supplied to the converter CAD, is normalized and represents the average value of the input analog signal SA. Referring to FIG. 1 again. The digital signal stored in the second memory M2 contains image information corresponding to one scan line stored in the first memory M1. At that time, since it is read out using the clock signal from the first clock generator CGI and then stored according to the clock signal from the second clock generator CG2, it is in a modulated form, that is, it is scaled. , In order to output the image information scaled in this way, the image processing combiator αM
The second memory controller MC2 may be energized to control and read the second memory M2. In other words, it is sufficient to display the memo IJM2 at a constant speed depending on the magnification or variable magnification.

First clock generator CGI and second clock generator C
Change the clock frequency in G2 to CKI, C
When N3 is assumed, the ratio of magnification is determined by the ratio of these image frequencies. Therefore, the number of pixels obtained by this digital signal converter is equal to (CN3 /CK
I) Double. Therefore, if the size of the image per -pixel is constant, the size of the image is (CN3 /
CKI') times.

That is, if the frequency CK2 of the second clock generator CG20 is made higher than the frequency CKI of the first clock generator CGI, the size of the image will be enlarged, and if the frequency is made lower, the size of the image will be reduced.

To change the magnification ratio, use the internal clock frequency CKI
, CN3. In that case, it is preferable to keep the other frequency constant. In particular, it is preferable to change the lower frequency -0. Furthermore, the frequency aC of the second clock generator CG2
If K2 is kept constant, the integral signal is changed to the clock frequency C
There is no need to normalize according to K2. Six to nine,
Converter CFV of integrator IL (see FIG. 2) and Loe variable gain amplifier AVG are no longer required. Also, if both the internal clock frequencies CKI and CN3 are made variable, and one is set to the print high frequency and the other is set based on that, the image can be enlarged.

- We have described the conversion of an image signal corresponding to one scanning line, which can be performed at high speed.
After the scaling in one direction is completed, if scaling is performed in the other direction, the scaling is completed both vertically and horizontally, and - iron transmission can be performed in a favorable state.In addition, the first clock is generated! Are CGI and 1g2 clock generator CG2 separate clock controllers? C.C.L.
However, output signals obtained by dividing one reference signal by different frequency division ratios may be used as the clock signal. In addition, using a phase-locked loop circuit (PLL), 1
one quasi-signal as Ik, two clock frequencies CK
I, CN3 may be obtained. If you configure it like this,
0. Figure 3 is a circuit diagram showing a specific example of the circuit w1 configuration in which the integrator IL and the converter CAD in the VC shown in Figure 1 are integrated. In FIG. 0, a sawtooth wave generator STG having the same circuit configuration as the integrating circuit ILG is installed. Input resistance 18 for the sawtooth Fukuha No. 8TW
A voltage dividing resistor RD1. It consists of a comparison circuit ccm consisting of RD2 and RD3 and corresponding comparators COMI, C0M2 and C0M3, and a logic section consisting of an inverter INV, a NAND gate, and an AND gate a.

Slip 70 tube FF output 1i! The integrated output signal SI of the analog signal 8A and the sawtooth ground wave signal S'IW are generated synchronously according to the signal (Q, Q). is compared with the comparison circuit CQM. Now, with the divided voltage of the sawtooth signal 8W as a reference, the voltage value of the sawtooth output signal 4SI is determined by each comparator C.
OMI.

The output of the comparison circuit COM and the output T of the converter CAD
The relationship between OI and TU2 is shown in the table below.
The analog signal SA is the digital signal SD2 (TOI,
TO2) K-converted 0 In this case, the average value of the image signal is N-converted regardless of the second clock frequency CK2.0 As described above, without changing the size of the pixels in the memory M1, the number of pixels is Since the image can be converted by changing the image size, and the magnification can be changed by changing the number of pixels without changing the pixel size compared to the same size, the input/output device is not limited, and image collection is easy. It is.

Thus, where the circuit IL is sent at the first rate, the present example is 8 without CDA, IL, CAD.
01 and S8 can also be directly connected to perform scaling conversion. Output the 4 digital image data from the memory M1 to the CGI node Co11, receive it by 0823 from CG2, and store it in the memory M2. This makes it possible to change the data of 0. When it is imported into Mc2, an error may occur, and noise may appear in the image.

On the other hand, in the above example, when there are densities from 0 to 7, the change point between 3 and 5 becomes 4. Therefore, a peak 1lII degree such as 7 will not be generated erroneously.

It is also possible to

Further, an image from a document reading element such as a CCD is shown in FIG. 5, which shows the operation of the computer shown in FIG. 1 in a flowchart. ft0M is the memory that stores the image data professional craftsmanship program.
b A memory storing image data or image data transmitted by facsimile s Ilo is a 1°1 round key to the 5x key, a CCD is connected to the print key,
This is an input/output boat to which a well-known laser beam printer LBP is connected as an output, and a well-known facsimile FX is connected as an input/output. The CPU is a central microprocessor that processes the RAM, Ilo, and image data processing section according to the program in the ROM.

It is assumed that one page of document image data, which has been scanned by a CCD, is stored in advance as the tone. When the scaling key is set to 1, the CPU reads it and (1) uses the clock controller CCL to multiply the frequency of the clock generator CG2 by 1 times that of CGI (if 2L Km is turned on, it is multiplied by 1 (8); If nothing is turned on, do the same as for CGt (4). Next, turn on the print key (5) and store 12 inches of image data in the RAM in the memory M1 (6).

Next, as described above, the memory controller MIC1 is operated and the clock generators CG, CG, CG are operated to perform the above-described image data adulteration processing, and the scaled image data is stored in the memo IJM2. When the photon is determined to be stored in M2 for one line (8), when the one-line multiplication process in RAM is completed, the data is scaled in the vertical direction, which was 5t4e during section M. Repeat the same process as above to double the number. When all is completed, the LBP can be controlled based on the RAM0 variable size data, and a desired variable size copy can be obtained. In this case, when performing processing in the vertical direction, press the keys again and operate the cyclic clock generator CG by operating keys , K,
It is also possible to make the ratio of I and CGI frequencies different from that in the horizontal direction.

If you get a one-way resized copy, then step 10.11
This can be obtained by controlling LBP (by the data in memory M2) without using the data in memory M2.

In this way, for example, it is possible to easily change the image density by changing the size of the image signal arbitrarily, it is also possible to change the size of halftones, and the edge processing of the image is performed with high precision and accuracy. Nashi,
It is also effective in connecting devices with different pixel densities, such as facsimile machines and laser printers.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the image conversion device according to the present invention, FIGS. 2 and 3 are detailed circuit diagrams in FIG. 1, FIG. 5 is a control flowchart in FIG. 1, and FIG.
The figure is a signal time chart in Figure 2, and in the figure M
1 and M2 are image data memories, CDA is a converter, and CGI-C (x is a clock generator. Applicant: Canon Inc.

Claims (1)

[Claims] means for serially outputting pixel data at a first speed;
and a means for changing the pixel ridges per line in response to a variable magnification input, and is configured to receive and re-output the above-mentioned elementary data at a speed of 2 different from the speed of 1 gl. conversion device.