JPH1023246A - Image-forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image-forming device by which an image with high image quality is obtained by avoiding missing of thin lines or deformed thin lines in the case of reduction. SOLUTION: This device is provided with a read-processing section 10 digitally reading an image, a control section 4 to set a reduction rate when an image data read by the read processing section 20, a reduction processing section 20 applying reduction processing to the image data read by the read processing section 10 based on the magnification set by the control section 4, a write processing section 30 conducting pulse width modulation based on the image data subjected to reduction processing by the reduction processing section 20 and wiring the pulse resulting data digitally, and a means forming an image based on the image data written by the write means. When the output pixels are divided to a plurality of very small pixels. Corresponding to each pulse width resulting from the width modulation by the write-processing section 30, the reduction processing section 20 conducts reduction processing by correcting the image data of a plurality of pixels into image data of one pixel, so that each very small pixel is made corresponding to the pixel read by the read- processing section 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image forming apparatus for reproducing an image by using PWM modulation, and more particularly, to data to be thinned out by lowering the number of output gradations per pixel and data to be left. And an image forming apparatus that collectively records the images in one pixel.

[0002]

2. Description of the Related Art An image forming apparatus for reproducing a digitally processed image by pulse width modulation includes a digital copying machine,
It is widely used in printers, facsimile machines, image scanners, and the like, and it is also widely practiced to reduce and reproduce a read image to a desired size and to store the image.

In such a conventional image forming apparatus, there is known a method of simply thinning out image data at predetermined intervals when a reduced image is generated.

On the other hand, Japanese Patent Application Laid-Open No. 2-302170 discloses that when a pixel to be decimated when performing reduction is an isolated pixel, one dot line disappears by shifting the pixel by one pixel and decimating it. There has been proposed an image forming apparatus which prevents the above. Further, Japanese Patent Application Laid-Open No. 5-9452
In Japanese Patent Publication No. 2 (1993), when two or more of the 2n pixels are black pixels, 1 / n simple thinning is performed, and when there is only one black pixel, each pixel is ORed and thinned to 1 / n. Thus, an image forming apparatus has been proposed in which one dot line is prevented from disappearing. Further, JP-A-7-87308 discloses that
Looking at the relationship between the pixel to be thinned and the adjacent pixel, when the two pixels to be thinned are a combination of white and black, if the pixel on the left is black, thin it as white, and if white, thin it as black. Such an image forming apparatus has been proposed.

[0005]

However, in the method of reducing the image by performing simple thinning and outputting the image, a thin line of about one pixel disappears due to thinning, or the white portion disappears, and the fine portion is crushed. There was a problem that was.

The image forming apparatus disclosed in Japanese Patent Laid-Open No. 2-302170 is not simple thinning,
When the image data at the thinning position is an isolated pixel, it is automatically shifted by one bit so that the isolated pixel is not thinned out.
It prevents the loss of characters and the crushing of small parts,
When black and white are continuous like fine characters, there is a problem that the disappearance or collapse of characters cannot be prevented. Further, the image forming apparatus disclosed in Japanese Patent Application Laid-Open No. 5-94522 performs a simple thinning of 1 / n when there are two or more black pixels in 2n pixels, and performs a simple thinning when there is only one. By taking OR of n pixels, black pixels are prevented from disappearing. However, when black and white continue in a fine character part, there is a problem that loss and collapse of characters cannot be prevented. Was. Further, Japanese Patent Application Laid-Open No.
The image forming apparatus disclosed in Japanese Patent No. 7308 refers to a pixel on the left when two pixels of interest to be thinned are a combination of black and white. If the pixel referred to is black, the thinning result is set to white. In the case of white, the thinning result is made black to prevent the disappearance and collapse of characters, but this is also the same as the invention described in the former two publications, and black and white in a fine character part is continuous. In such a case, there is a problem that a satisfactory result cannot be obtained.

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances of the prior art, and an object of the present invention is to provide an image forming apparatus capable of obtaining a high-quality image by eliminating disappearance or collapse of a thin line when reducing. To provide.

[0008]

To achieve the above object, a first means is a means for digitally reading an image,
Means for setting a reduction rate when outputting image data read by the reading means; means for reducing the image data read by the reading means based on the magnification set by the means for setting the reduction rate; Image forming apparatus comprising: means for performing pulse width modulation based on image data reduced by means for reducing processing and writing digitally; and means for forming an image based on image data written by the writing means In the means for performing the reduction processing, when dividing the output pixel into a plurality of fine pixels corresponding to each pulse width pulse width modulated by the writing means, each fine pixel read by the reading means and the pixel read by the reading means respectively Correspondingly, reduction processing is performed by combining image data of a plurality of pixels into image data of one pixel. It is characterized in that.

[0009] To achieve the above object, the second means is as follows.
The means for performing the reduction processing in the first means reduces the image data of a plurality of pixels to one by reducing the number of output gradations of each pixel.
It is characterized in that image data in a pixel is collected.

[0010] To achieve the above object, a third means is as follows.
When the number of gray levels that can be output by the second means is greater than the number of output gray levels per pixel, a plurality of pixel data are combined into one pixel without reducing the number of output gray levels of each pixel. It is characterized by.

The fourth means is characterized in that, in the first to third means, a signal indicating reduced data is added to a predetermined bit position of the reduced image data.

The fifth means is characterized in that the signal in the fourth means is added to the most significant bit of the image data.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a digital copying machine according to an embodiment of the present invention;

FIG. 2 is a perspective view showing the appearance of the digital copying machine. In FIG. 1, the digital copying machine 1 is provided with a document table 2 for placing and reading a document thereon and a pressure plate 3 for pressing the document on the top, and when the pressure plate 3 is located on the document table 2, the digital plate 1 An operation unit 4 that is not covered is provided on the upper part of the digital copying machine 1. In the operation unit 4,
A mode for reading a document, setting of a copy magnification, display to an operator, and the like are performed. A paper feeding unit 5 is provided at a lower portion of the main body of the digital copying machine 1, and a paper discharging unit 6 is provided at a left side surface. The inside of the digital copying machine 1 includes an exposure optical system, a paper feeding and conveying system, a developing system, a fixing system, and a paper discharging system (both not shown)
A well-known mechanism and control device are provided to realize the operation as a copying machine.

That is, an original (not shown) is placed on the original table 2, and the original is brought into close contact with the original table 2 by the pressure plate 3, and then, according to an instruction from the operation unit 4, an illumination system (not shown) The original is read by the optical system. After performing various corrections on the read image data, the laser beam is modulated by a writing system (not shown) based on the image data, and an electrostatic latent image is formed on a photoconductor (not shown). Thereafter, a copy image is formed on a sheet fed from the sheet feeding unit 5 through a so-called electrophotographic process.

A schematic configuration of an image data processing portion used in the digital copying machine 1 according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the image data processing unit.

The image data processing unit is a reading processing unit 1
0, reduction processing unit 20, writing processing unit 30, control unit 40
And the operation unit 4 described above. The reading processing unit 10 performs various corrections such as shading correction on image data read by a CCD line sensor (not shown) at, for example, 400 dpi, and obtains 6 bits per pixel as image data D (64 gradations: 0 / 63- 63/6
In 3), output to the reduction processing unit 20. The reduction processing unit 20 outputs to the writing processing unit 30 reduced image data that has been subjected to thinning and data correction as described later and a thinning signal indicating at which position the thinning processing has been performed. In the write processing unit 30, the laser diode is subjected to PWM (pulse width modulation, hereinafter referred to as "PWM modulation") based on the reduced image data and the thinning signal input from the reduction processing unit 20.
The operation is controlled by the signal modulated in step (1) to write the image on the photoconductor. The control unit 40 is connected to the operation unit 4 and, based on a mode for reading a document set by the operation unit 4, setting of a reduction ratio, and the like, the reading processing unit 10, the reduction processing unit 20, and the writing processing unit 30. Control. Since a known technique can be used as it is for the reading processing unit 10, detailed description is omitted.

Next, a detailed configuration of the reduction processing section 20 of FIG. 1 will be described with reference to FIGS. 3 is a block diagram showing the configuration of the reduction processing unit 20, FIG. 4 is a block diagram showing the configuration of the data correction unit in FIG. 3 in detail, and FIG. 5 is a relationship between a clock pulse and image data in the data correction unit in FIG. FIG. 6 is a block diagram showing the configuration of the thinning-out processing unit in FIG. 1 in detail, and FIG.
8 is a time chart for explaining the relationship between the clock pulse and the image data in the thinning-out processing unit in FIG. 6, FIG. 8 is a block diagram showing the configuration of the read / write clock generation unit in FIG. 1 in detail, and FIG. 3 is a block diagram showing a detailed configuration of a combinational circuit in FIG.

As shown in FIG. 3, the reduction processing section 20 includes a data correction section 21, a thinning processing section 22, and a read / write clock generation section 23. The image data D is input from the reading processing unit 10 to the data correction unit 21, and the image data to be thinned out according to the reduction ratio set by the operation unit 4 in the data correction unit 21 and the image data D A correction process is performed to reduce the number of tones (bits) per pixel of the image data thus obtained and combine them into one pixel. In the thinning processing unit 22, the data correction unit 21
Then, reduced image data is generated by thinning out the image data after the correction processing input from the base station based on the set reduction ratio. In the read / write clock generator 23, the thinning signal and the thinning processor 2 used in the data corrector 21 are used.
2 generates a read / write clock to be used.

Next, the detailed configuration and operation of the data correction unit 21 will be described with reference to FIGS. The data correcting section 21 thins out the image data in the thinning processing section 22 based on the 6-bit image data D output from the reading processing section 10 and a thinning signal generated by a read / write clock generating section 23 described later. Before this, data is stored by reducing the number of gradations (the number of bits) into a plurality of pixels and combining them into one pixel. The data correction unit 21 includes three flip-flops (hereinafter, referred to as F / F) 211, 212, and 213 as shown in FIG.
And a selector 214.

The operation of the data correction unit 21 will now be described with reference to FIG.
This will be described in detail with reference to the time chart of FIG. Image data D as shown in FIG. 5B from the read processing unit 10 is latched by the F / F 211 at the rising edge of the basic clock pulse shown in FIG. The image data is aligned, and the output is as shown in FIG. The output of the F / F 211 is further latched by the F / F 212, and becomes an output as shown in FIG. At the same time, the F / F 213 latches and outputs the upper 3 bits of each of the image data of the adjacent two pixels aligned on the same time. That is, F / F
The output of 213 is image data in which the number of gradations of two adjacent pixels is reduced from 6 bits to 3 bits and combined into one pixel, as shown in FIG. In the selector 214, the normal image data as shown in FIG. 5D output from the F / F 212 based on the thinning signal and the F / F 213
The image data as shown in FIG. 5 (e), which has been corrected to combine the two pixels output from, into one pixel, is selected and output. In this embodiment, as shown in FIG. 5F, the thinning signal is set to 50%. In this case, as shown in FIG. Image data in which two pixels are combined into one pixel is output alternately.

Next, reduction processing, that is, the thinning processing section 22
Will be described. Thinning-out processing unit 22
6, as shown in FIG. 6, memories 221 and 222, a write address counter 223, a read address counter 22
4. It comprises address switching means 225 and 226, data switching means 227 and 228 and F / Fs 229 and 230. Reduction processing is performed on the memories 221 and 222.
This is realized by intermittently controlling the increment of the write address with respect to. That is, the increment of the write address is intermittently controlled by thinning out the write clock pulse of the write address counter 223, and the image data output from the data correction unit 21 and the read / write clock generation unit 23 are output twice to the same write address. The output thinning signal is stored in the memory 221 or 223.
Write to. As a result, since one pixel data is overwritten on several pixels, the overwritten data is thinned out and the image is reduced. Also, the decimated signal is similarly reduced.

The operation of the thinning processing section 22 will be described in more detail with reference to FIG. 7. FIG. 7A shows the same basic clock as FIG. 5A, and FIG. 7B shows the data correction section. 21
5 (g) in FIG. Since the reduction ratio is 50% as described above, the thinned signal is as shown in FIG. 7C. That is, in this case, FIG.
As shown in FIG. 7D, the write address is intermittently controlled as shown in FIG. 7E by thinning out the write clock pulse by one clock pulse for every two clock pulses. As a result, one pixel is thinned out for two pixels. , The amount of image data is reduced by half, and the thinning signal is reduced accordingly. When the memory 221 is performing a read operation, the memory 223 causes the address switching means 225 and 226 to perform the write operation so that the write address counter 2 performs the write operation.
23. The output of the read address counter 224 is switched to supply an address to the memories 221 and 222. Also,
The image data and the thinning signal are also switched by the data switching means 227,
228, the image data and the thinning signal read out from the memories 221 and 222 are input to the F / F 22.
The data is latched at 9, 230 and output to the write processing unit 30 as reduced image data as shown in FIG. The read clock pulse has a waveform as shown in FIG. 7 (f), and a read address is supplied in synchronization with the read clock pulse as shown in FIG. 7 (g). At this time, when the memory 221 is writing, the output of the F / F 229 and the output of the data switching means 228 become high impedance so that the image data output from the memory 221 or 223 does not collide with the input data from the data correction unit 21. And when the memory 221 is reading, the output of the F / F 230 and the data switching means 227 is set to a high impedance.

The read / write clock generator 23 includes F / Fs 231 and 237 and an adder 23, as shown in FIG.
2, a comparator 233, a subtractor 234, a selector 225, and a combination circuit 236. Next, a thinning control method by the read / write clock generator 23 will be described.

The output of the F / F 231 is input to one input terminal A of the adder 232 of the read / write clock generating unit 23, and the other input terminal B is input from the control unit 40 of FIG. The value set according to is input. Now, when the set magnification is, for example, 50%, the set value from the control unit 40 is 500 (in hexadecimal notation, 1F4) from (set value) ＝ 1000 = 0.5 (= 50%). Hereafter, 1
When it is expressed by a hexadecimal number, H is written at the end, and when it is expressed by a binary number, B is written at the end. ) Is set.

Since the output terminal Q of the F / F 231 is initially cleared by the data valid signal, the output terminal Q is 000H regardless of the value of the input terminal D. The control unit 40 applies 000H and 1F4H, which is a set value corresponding to the magnification, to the other input terminal B. Therefore, the output terminal [A + B] of the adder 232 is 1F4H. This output terminal [A + B] of the adder 232 is connected to one input terminal A of the comparator 233, and the other input terminal B of the comparator 233.
Has a fixed value of 3E8H (1000), the output terminal [A <B] of the comparator 233 goes high. The output terminal [A + B] of the adder 232 is also connected to the input terminal B of the selector 235 and the input terminal B of the subtractor 234. The other input terminal A of the selector 235 is connected to the output terminal [BA] of the subtractor 234, and the selection input terminal S of the selector 235 is connected to the comparator 2
33 output terminals [A <B] are connected. Therefore, when the selection input terminal S of the selector 235 is at a high level, the value (1F4H) input to the input terminal B of the selector 235 is output. Output terminal Y of selector 235
Is connected to the input terminal D of the F / F 231, and the output of the selector 235 is latched by the reference clock pulse in the F / F 231, and the adder 23 is output in the next cycle.
Used for addition by two.

In the next cycle, the output of the output terminal [A + B] of the adder 232 is 3E8H (1F4H + 1F4H).
Therefore, the output terminal [A <B] of the comparator 233 becomes low level. Thereby, the output of the selector 235 becomes
Since what is input to the input terminal A is output, the output of the subtractor 234 becomes the output of the selector 235. Subtractor 2
The input terminal A of the subtractor 234 is fixed at 3E8H, which is a fixed value. Therefore, both inputs become 3E8H, and as a result, the output terminal [BA] of the subtractor 234 becomes 000H, and the output of the selector 235 becomes 000H. Becomes Hereinafter, by continuing this operation, the output of the comparator 233 alternates between a high level and a low level alternately for each clock pulse, and uses this as a thinning signal. This thinning signal is latched by the basic clock by the F / F 237 and output to the data correction unit 21.

That is, in the read / write clock generating section 23, the set values set according to the magnification by the control section 40 are successively added, and while the value is less than 1000, the high level signal is output from the comparator 233. , And outputs a low-level signal when the value is 1000 or more. When the output of the adder 232 becomes 1000 or more, the subtractor 234 subtracts 1000 from the value and adds the set value again.

A combination circuit 236 that outputs a write clock pulse and a read clock pulse to the thinning processing section 22 based on the thinning signal and the basic clock pulse output to the comparator 233, as shown in FIG. , And AND gate 242. That is, the thinned signal is transmitted to the delay line circuit 2
By shifting the timing by 41 to match the phase with the basic clock pulse and by taking the logical product with the AND gate 242, a clock pulse thinned out from the clock pulse can be obtained. Thereafter, the thinned clock pulse is used as a write clock pulse, the basic clock pulse is used as a read clock pulse, and the output terminal W
What is necessary is just to output from C and RC to the thinning-out processing part 22. Note that the write clock pulse and the read clock pulse are shown in (d) and (f) of FIG.

Next, the detailed configuration of the write processing unit 30 in FIG. 1 will be described with reference to FIGS. FIG.
FIG. 1 is a block diagram showing the configuration of the write processing unit in detail;
1 is a block diagram showing a detailed configuration of a write level conversion unit in FIG. 10, FIG. 12 is a diagram showing a relationship between reduced image data and gradation level data in the write level conversion unit in FIG. 11, and FIG. FIG. 14 is a waveform diagram showing a relationship between a pulse generated by a pulse generation unit and a pixel.
FIG. 6 is a diagram for explaining a relationship between a pulse selected by one pulse selection unit and a pixel.

First, based on FIG.
0 will be described. The write processing unit 30 includes a write level conversion unit 301, a laser diode (hereinafter, a laser diode).
The write level conversion unit 301 includes a control unit 302 and an LD 303. The write level conversion unit 301 uses the LD 303 to store an electrostatic latent image on a photoconductor (not shown) based on the image data reduced by the reduction processing unit 20. In order to form an image, the reduced decimated data is converted into a PWM signal. In the LD control unit 32, the write level conversion unit 31
The LD 33 is controlled by the PWM signal based on the PWM signal
Although the M modulation is performed, since this portion is not unique to the present invention, a detailed description is omitted.

The write level conversion section 31 has a data conversion ROM 311 as shown in FIG.
It comprises a pulse selector 312 and a pulse generator 313.

The data conversion ROM 311 stores the data in the reduction processing unit 2.
The image data which has been reduced by the thinning processing unit 22 within 0 is converted into gradation level data based on the reduced thinning signal. That is, with the reduced image data and the reduced thinning signal as addresses, a preset gradation level is written at the location indicated by the address, and the gradation level is changed to the corresponding gradation level. A specific example will be described with reference to FIG. 12. FIG. 12A shows a correspondence relationship between reduced image data and gradation level data when the reduced thinning signal is at a low level, and FIG. () Shows the correspondence between the reduced image data and the gradation level data when the reduced thinning signal is at the high level. From these figures, assuming now that the reduced image data is 48 (110000B), when the level of the reduced-thinned-out signal is low, the gradation level is set to 06H (FIG. 12A). 00
The data has been written so as to become “00110B). When the reduced-thinned-out signal is at the high level, the upper and lower three bits of the reduced image data (for each image data) are viewed from FIG. Note that the gray level data when the thinning signal is at a high level starts with 1, and the gray level data 3 corresponding to the upper and lower 3 bits of the reduced image data.
Each has a bit. Therefore, in this example, 7
(111B) and 0 (000B), the gradation level data corresponding to each image data is 4H and 0H.
Therefore, the data conversion ROM 311 has a total of 60
Data is written so that H (1100000B) is output. Here, the most significant bit is used to discriminate whether it is data of one pixel or data obtained by combining two pixels into one pixel. If the most significant bit is 0, it is data of one pixel, and if the most significant bit is 1, it is two pixels Can be distinguished from data collected in one pixel. That is, the thinning signal is H
In this case, the gradation level data starts with 1, and the gradation level data corresponding to the upper and lower 3 bits of the reduced image data follows.

Next, the pulse generator 313 will be described with reference to FIG. The pulse generator 313 first generates signals a to h by shifting the basic clock and its inverted signal to a delay line or the like. Then, two of the signals a to h are combined by an OR gate or an AND gate to obtain (A) to (W).
13 kinds of signals are generated. The reason why such a PWM signal is generated in the pulse generator 313 is to divide one pixel into eight and obtain nine output gradations as shown in the lowermost part of FIG.

The pulse selecting section 312 includes the pulse generating section 31
3 is selected based on the gradation level data converted by the data conversion ROM 311. FIGS. 14A and 14B show the selection of the PWM signal when the above-mentioned reduced image data is 48. FIG. 14A shows the case where the reduced-thinning signal is at the low level, and FIG. 14B shows the case where the reduced-thinning signal is at the high level. I have. That is, when the reduced image data is 48 and the reduced thinning signal is at low level, the gradation level data is 06.
Since the signal becomes H, the PWM signal is configured so that the signal shown in FIG. Further, when the reduced thinning signal is at the high level, the gradation level data is 60H, so that at this time, a signal in which the ORs of (a) and (e) of FIG. 13 are taken is selected.

The effect of the embodiment of the present invention described above will be described on an actual image with reference to FIG. 15 while comparing it with the case of simply thinning out or the problem of the conventional method. FIG. 15 is an explanatory diagram for specifically explaining the thinning according to the conventional method and the thinning according to the present embodiment.

FIG. 15A shows the image data read by the reading processing unit 10. When the image data in (a) is reduced by 50%, if every other pixel is simply thinned out, the result on the right side of (b) or the result on the left side in (b) can be obtained. The result of converting this (b) into the gradation level data is as shown on the left side of (c) in the case of the result on the left side, and when this is PWM-modulated and actually output,
As shown on the left side of (d), the white portion disappears, and the characters are crushed. Conversely, if the thinned-out result is as shown on the right side of (b), the result of conversion to the gradation level data is as shown on the right side of (c), and when it is PWM-modulated and actually output, As shown on the right side of (d), data is lost.

In order to prevent the disappearance of characters as shown on the right side of FIG. 15, it has been conventionally proposed to prevent the disappearance of black isolated points, but the thinned out result is shown in the left side of FIG. , And when PWM modulation is actually performed, the result is as shown on the left side of (d), and character collapse cannot be prevented.

On the other hand, in the present embodiment, the result of thinning out the data by 50% in the same manner is as shown in FIG. 15E because the upper 3 bits of each data are combined into one pixel. become. That is, “0” at the left end of (a)
Is represented by 6 bits, "000000", and "6" on the right is represented by 6 bits, "000110".
These two upper 3 bits are both "000", and both are "0" in decimal. Also, if the third “56” from the left in (a) is represented by 6 bits, “1110” is obtained.
00, and "5" on the right is represented by 6 bits, "000101", and the upper 3 bits are "1".
"11" and "000", and "7" and "0" in decimal. As shown in (e), the result of the reduced image data thus obtained is “0 and 0”, “7 and 0”,
"7 and 0". If the result of (e) is represented by a hexadecimal number with the highest (seventh) bit of the gradation level being 1, the result is as shown on the right side of (f) of FIG. Excluding the upper and lower 3 bits, the result is as shown on the left. Then, the result is subjected to PWM modulation, and the result of actual image output is (g)
become that way.

As can be seen from (g), character collapse and disappearance as in the conventional method do not occur, and the line width obtained as a result of further scaling is reduced by 50% from the original line width. , The advantage is that the reproducibility of the concentration can be improved.

[0041]

As is clear from the above description, according to the first aspect of the present invention, the image data read by the reading means is not reduced by thinning it out, but a plurality of pixels are reduced. Since the image data is collectively recorded as image data of one pixel, disappearance or collapse of a thin line at the time of reduction is eliminated, and a high-quality image can be obtained. In addition, since the reduction ratio can also obtain a line width that is approximately proportional, the density reproducibility can be improved.

According to the second aspect of the present invention, the number of output gradations of each pixel is partially reduced to combine a plurality of image data into one pixel. Thus, a high quality image can be obtained.

According to the third aspect of the present invention, if the number of output gradations is larger than the number of output gradations of each pixel, the output gradation number of each pixel is kept as it is and a plurality of image data are converted to one pixel. Since it is possible to collectively reduce the size of the image, it is possible to eliminate the disappearance or collapse of the thin line and obtain a high-quality image.

According to the fourth and fifth aspects of the present invention, whether or not the image data is reduced is incorporated in the data indicating the gradation level, so that good density reproducibility can be obtained only by reproducing the image data. Can be demonstrated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image data processing unit according to an embodiment of the present invention.

FIG. 2 is a perspective view showing an appearance of a digital copying machine to which the present invention is applied.

FIG. 3 is a block diagram illustrating a configuration of a reduction processing unit in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration of a data correction unit in FIG. 3 in detail;

FIG. 5 is a time chart for explaining a relationship between a clock pulse and image data in a data correction unit in FIG. 4;

FIG. 6 is a block diagram illustrating a configuration of a thinning-out processing unit in FIG. 3 in detail.

7 is a time chart for explaining a relationship between a clock pulse and image data in a thinning-out processing unit in FIG. 6;

FIG. 8 is a block diagram showing in detail a configuration of a read / write clock generator in FIG. 3;

FIG. 9 is a block diagram illustrating a detailed configuration of a combinational circuit in FIG. 8;

FIG. 10 is a block diagram illustrating a configuration of a write processing unit in FIG. 1 in detail;

11 is a block diagram illustrating a detailed configuration of a write level conversion unit in FIG.

FIG. 12 is a diagram illustrating a relationship between reduced image data and gradation level data in a write level conversion unit in FIG. 11;

FIG. 13 is a waveform diagram showing a relationship between a pulse generated by the pulse generator of FIG. 11 and a pixel.

FIG. 14 is a diagram for explaining a relationship between a pulse selected by a pulse selection unit in FIG. 11 and a pixel;

FIG. 15 is an explanatory diagram for specifically explaining thinning-out according to the present embodiment and thinning-out according to the present embodiment.

[Explanation of symbols]

 Reference Signs List 4 operation unit 10 read processing unit 20 reduction processing unit 21 data correction unit 22 thinning processing unit 23 read / write clock generation unit 30 write processing unit 40 control unit 31 write level conversion unit 32 LD control unit 33 LD

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 1/409 H04N 1/40 101D

Claims (5)

[Claims] 1. An image reading apparatus comprising: means for digitally reading an image; means for setting a reduction rate when outputting image data read by the reading means; means for setting the reduction rate for image data read by the reading means. Means for performing reduction processing based on the set magnification, means for performing pulse width modulation based on image data reduced by the reduction processing means, digitally writing means, and image data written by the writing means. In the image forming apparatus provided with means for forming an image based on the, when the reduction processing means, when dividing the output pixels into a plurality of fine pixels corresponding to each pulse width pulse width modulated by the writing means, The image data of a plurality of pixels is set to 1 by associating each fine pixel with the pixel read by the reading unit. Image forming apparatus characterized by reduced processing by assembling the elements of the image. 2. The image processing apparatus according to claim 1, wherein the reducing unit converts the image data of the plurality of pixels into one by reducing the number of output gradations of each pixel.
The image forming apparatus according to claim 1, wherein the image data is collected into image data in pixels. 3. The reduction processing means according to claim 1, wherein, when the number of outputable tones is larger than the number of output tones per pixel, the image data of a plurality of pixels is output without reducing the number of output tones of each pixel. 3. The image forming apparatus according to claim 2, wherein the image data is collected into image data within one pixel. 4. The image according to claim 1, wherein a signal indicating the reduced data is added to a predetermined bit position of the reduced image data. Forming process. 5. The image forming apparatus according to claim 4, wherein the signal is added to the most significant bit of the image data.