KR920022487A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR920022487A
KR920022487A KR1019910007210A KR910007210A KR920022487A KR 920022487 A KR920022487 A KR 920022487A KR 1019910007210 A KR1019910007210 A KR 1019910007210A KR 910007210 A KR910007210 A KR 910007210A KR 920022487 A KR920022487 A KR 920022487A
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KR
South Korea
Prior art keywords
insulating film
substrate
region
silicon layer
forming
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KR1019910007210A
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Korean (ko)
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KR930006731B1 (en
Inventor
김윤기
반천수
김병렬
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019910007210A priority Critical patent/KR930006731B1/en
Publication of KR920022487A publication Critical patent/KR920022487A/en
Application granted granted Critical
Publication of KR930006731B1 publication Critical patent/KR930006731B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Abstract

내용 없음.No content.

Description

반도체 장치의 소자 분리 방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 제조공정도.2 is a manufacturing process diagram according to the present invention.

Claims (9)

제1도전형의 반도체 기판과, 상기 기판내에 소자영역과 소자분리영역을 구비하는 반도체 장치의 소자 분리 방법에 있어서, 상기 기판 상면에 제1절연막과 비정질 실리콘층을 순차적으로 형성한 후 열처리 공정을 실시하여 상기 비정질 실리콘을 다결정 실리콘화하는 제1공정과, 상기 기간 상면에 제2절연막을 형성한 다음 상기 소자분리 영역에 해당하는 상기 제2절연막을 선택적으로 제거하는 제2공정과, 상기 제2절연막이 제거된 영역을 선택적으로 산화시키는 제3공정을 구비함을 특징으로 하는 반도체 장치의 소자 분리 방법.A device isolation method for a semiconductor device having a first conductive semiconductor substrate and an element region and an element isolation region in the substrate, wherein the first insulating film and the amorphous silicon layer are sequentially formed on the upper surface of the substrate and then subjected to a heat treatment process. Performing a first process of forming polycrystalline silicon of the amorphous silicon; forming a second insulating film on the upper surface of the period; and then selectively removing the second insulating film corresponding to the device isolation region. And a third step of selectively oxidizing the region from which the insulating film has been removed. 제1항에 있어서, 상기 비정질 실리콘층이 약 550℃ 이하의 온도에서 저압화학기상 증착법으로 형성됨을 특징으로 하는 반도체 장치의 소자 분리 방법.The method of claim 1, wherein the amorphous silicon layer is formed by low pressure chemical vapor deposition at a temperature of about 550 ° C. or less. 제1항에 있어서, 상기 제1공정의 열처리 공정이 1000℃ 이상의 온도에서 질소분위기로 실시됨을 특징으로 하는 반도체 장치의 소자 분리 방법.The method of claim 1, wherein the heat treatment process of the first process is performed at a temperature of 1000 ° C. or higher in a nitrogen atmosphere. 제1항에 있어서, 상기 제2공정후 상기 기판 상부로 부터 제1도전형의 불순물을 이온주입하여 상기 제2절연막이 제거된 기판 영역에 채널 스톱 영역을 형성하는 공정을 더 구비함을 트징으로 하는 반도체 장치의 소자 분리 방법.The method of claim 1, further comprising: forming a channel stop region in the substrate region from which the second insulating layer is removed by ion implanting impurities of a first conductivity type from the upper portion of the substrate after the second process. A device isolation method for a semiconductor device. 제4항에 있어서, 상기 제3공정후 상기 제2절연막과 열처리에 의한 다결정 실리콘층 및 제1절연막을 순차적으로 제거하는 공정을 더 구비함을 특징으로 하는 반도체 장치의 소자 분리 방법.5. The method of claim 4, further comprising sequentially removing the second insulating film, the polycrystalline silicon layer and the first insulating film by heat treatment after the third step. 제1항에 있어서, 상기 제1절연막이 200-500Å 두께의 산화막임을 특징으로 하는 반도체 장치의 소자 분리 방법.The method of claim 1, wherein the first insulating layer is an oxide layer having a thickness of 200-500 Å. 제6항에 있어서, 상기 제2절연막이 100-200Å 두께의 절화막임을 특징으로 하는 반도체 장치의 소자 분리 방법.7. The method of claim 6, wherein the second insulating film is a cutout film having a thickness of 100-200 microns. 제1항에 있어서, 상기 제1공정후 상기 기판 상면에 다결정 실리콘층을 형성하는 공정을 더 구비함을 특징으로 하는 반도체 장치의 소자 분리 방법.2. The method of claim 1, further comprising forming a polycrystalline silicon layer on an upper surface of the substrate after the first step. 제8항에 있어서, 상기 다결정 실리콘층의 두께가 200-500Å임을 특징으로 하는 반도체 장치의 소자 분리 방법.9. The method of claim 8 wherein the thickness of the polycrystalline silicon layer is 200-500 GPa. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910007210A 1991-05-03 1991-05-03 Isolation method of semiconductor device KR930006731B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910007210A KR930006731B1 (en) 1991-05-03 1991-05-03 Isolation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910007210A KR930006731B1 (en) 1991-05-03 1991-05-03 Isolation method of semiconductor device

Publications (2)

Publication Number Publication Date
KR920022487A true KR920022487A (en) 1992-12-19
KR930006731B1 KR930006731B1 (en) 1993-07-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007210A KR930006731B1 (en) 1991-05-03 1991-05-03 Isolation method of semiconductor device

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KR930006731B1 (en) 1993-07-23

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